Inventor · disambiguated record
Siddhartha Chatterjee
Also filed as: CHATTERJEE SIDDHARTHA
8 granted patents·6 pending applications·186 citations·filing 1993–2025
86Inventor score
Top patents by PatentIndex Score
14 records- 0196US7954094B2Method for improving performance of executable codeIBM·Filed 2006·Granted May 31, 2011·63 cites·79 claims
- 0274US5475842AMethod of compilation optimization using an N-dimensional template for relocated and replicated alignment of arrays in data-parallel programs for reduced data communication during executionXEROX CORP·Filed 1993·Granted Dec 12, 1995·68 cites·1 claims
- 0371US7380086B2Scalable runtime system for global address space languages on shared and distributed memory machinesIBM·Filed 2003·Granted May 27, 2008·22 cites·8 claims
- 0460US2025356558A1Computing Systems and Methods for Generating Media Content Using a Multi-Agent ArchitecturePROCORE TECH INC·Filed 2025·Application pending·0 cites
- 0558US7555604B2Method and structure for an improved data reformatting procedureIBM·Filed 2006·Granted Jun 30, 2009·1 cites·20 claims
- 0655US2025337275A1Augmented reality-based smart socket visualizationHONEYWELL INT INC·Filed 2025·Application pending·0 cites
- 0753US5450313AGenerating local addresses and communication sets for data-parallel programsXEROX CORP·Filed 1994·Granted Sep 12, 1995·29 cites·5 claims
- 0852US2025336277A1Integrating a fire alarm system with smart electrical sockets of a facilityHONEYWELL INT INC·Filed 2025·Application pending·0 cites
- 0945US8055878B2Method and structure for skewed block-cyclic distribution of lower-dimensional data arrays in higher-dimensional processor gridsIBM·Filed 2005·Granted Nov 8, 2011·0 cites·20 claims
- 1043US7596680B2System and method for encoding and decoding architecture registersIBM·Filed 2003·Granted Sep 29, 2009·0 cites·4 claims
- 1142US2006179240A1System and method for algorithmic cache-bypassIBM·Filed 2005·Application pending·0 cites
- 1242US2006167836A1Method and structure for algorithmic overlap in parallel processing for exploitation when load imbalance is dynamic and predictableIBM·Filed 2005·Application pending·0 cites
- 1341US8200945B2Vector unit in a processor enabled to replicate data on a first portion of a data bus to primary and secondary registersCHATTERJEE SIDDHARTHA·Filed 2003·Granted Jun 12, 2012·3 cites·14 claims
- 1441US2006168401A1Method and structure for high-performance linear algebra in the presence of limited outstanding miss slotsIBM·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →