Inventor · disambiguated record
Siddharth Chouksey
Also filed as: CHOUKSEY SIDDHARTH
21 granted patents·20 pending applications·16 citations·filing 2016–2024
90Inventor score
Top patents by PatentIndex Score
41 records- 0195US12272727B2Gate-all-around integrated circuit structures having embedded GeSnB source or drain structuresINTEL CORP·Filed 2024·Granted Apr 8, 2025·2 cites·19 claims
- 0294US11990513B2Gate-all-around integrated circuit structures having embedded GeSnB source or drain structuresINTEL CORP·Filed 2022·Granted May 21, 2024·2 cites·20 claims
- 0393US11222977B2Source/drain diffusion barrier for germanium NMOS transistorsINTEL CORP·Filed 2017·Granted Jan 11, 2022·8 cites·22 claims
- 0486US11532706B2Gate-all-around integrated circuit structures having embedded GeSnB source or drain structuresINTEL CORP·Filed 2019·Granted Dec 20, 2022·3 cites·28 claims
- 0582US12255234B2Integrated circuit structures having germanium-based channelsINTEL CORP·Filed 2024·Granted Mar 18, 2025·0 cites·11 claims
- 0680US12119387B2Low resistance approaches for fabricating contacts and the resulting structuresINTEL CORP·Filed 2020·Granted Oct 15, 2024·1 cites·10 claims
- 0776US2025107174A1Neighboring gate-all-around integrated circuit structures having conductive contact stressor between epitaxial source or drain regionsINTEL CORP·Filed 2024·Application pending·0 cites
- 0875US11923421B2Integrated circuit structures having germanium-based channelsINTEL CORP·Filed 2022·Granted Mar 5, 2024·0 cites·3 claims
- 0971US11699756B2Source/drain diffusion barrier for germanium nMOS transistorsINTEL CORP·Filed 2021·Granted Jul 11, 2023·0 cites·20 claims
- 1068US11735670B2Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium NMOS transistorsINTEL CORP·Filed 2021·Granted Aug 22, 2023·0 cites·20 claims
- 1165US12199142B2Neighboring gate-all-around integrated circuit structures having conductive contact stressor between epitaxial source or drain regionsINTEL CORP·Filed 2020·Granted Jan 14, 2025·0 cites·20 claims
- 1264US2022109072A1Reducing band-to-band tunneling in semiconductor devicesINTEL CORP·Filed 2021·Application pending·0 cites
- 1360US11437472B2Integrated circuit structures having germanium-based channelsINTEL CORP·Filed 2018·Granted Sep 6, 2022·0 cites·20 claims
- 1459US2025212441A1Incorporation of semiconductor doping materials in metal contacts via reactive sputteringINTEL CORP·Filed 2023·Application pending·0 cites
- 1557US2025212507A1Cmos metal contacts with dopant diffusion barriersINTEL CORP·Filed 2023·Application pending·0 cites
- 1657US2025311311A1Source and drain structures providing highly conductive contact interface and strain to mosfet channelINTEL CORP·Filed 2024·Application pending·0 cites
- 1757US2025220958A1Source/drain contact trench with dielectric liner on contact metalINTEL CORP·Filed 2023·Application pending·0 cites
- 1856US2022199773A1Condensed source or drain structures with high germanium contentINTEL CORP·Filed 2020·Application pending·0 cites
- 1955US11233148B2Reducing band-to-band tunneling in semiconductor devicesINTEL CORP·Filed 2017·Granted Jan 25, 2022·0 cites·25 claims
- 2054US12414339B2Formation of gate spacers for strained PMOS gate-all-around transistor structuresINTEL CORP·Filed 2021·Granted Sep 9, 2025·0 cites·20 claims
- 2154US11923290B2Halogen treatment for NMOS contact resistance improvementINTEL CORP·Filed 2020·Granted Mar 5, 2024·0 cites·14 claims
- 2254US11189730B2Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium nMOS transistorsINTEL CORP·Filed 2017·Granted Nov 30, 2021·0 cites·20 claims
- 2353US12266570B2Self-aligned interconnect structures and methods of fabricationINTEL CORP·Filed 2020·Granted Apr 1, 2025·0 cites·20 claims
- 2452US12328927B2Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structuresINTEL CORP·Filed 2020·Granted Jun 10, 2025·0 cites·20 claims
- 2552US2024105508A1Integrated circuit devices with contacts using nitridized molybdenumINTEL CORP·Filed 2022·Application pending·0 cites
- 2652US2024006506A1Low-resistance and thermally stable contacts with phosphide or arsenide metal compound layersINTEL CORP·Filed 2022·Application pending·0 cites
- 2751US2024006488A1Capping source and drain regions of transistors to prevent diffusion of dopants during fabricationINTEL CORP·Filed 2022·Application pending·0 cites
- 2850US2024006494A1Source and drain refractory metal capINTEL CORP·Filed 2022·Application pending·0 cites
- 2950US2024006533A1Low-resistance and thermally stable contacts with boride, indium, or gallium metal compound layersINTEL CORP·Filed 2022·Application pending·0 cites
- 3049US11450739B2Germanium-rich nanowire transistor with relaxed buffer layerINTEL CORP·Filed 2018·Granted Sep 20, 2022·0 cites·20 claims
- 3149US10644112B2Systems, methods and devices for isolation for subfin leakageINTEL CORP·Filed 2016·Granted May 5, 2020·0 cites·19 claims
- 3248US2023187553A1Metal carbon barrier region for nmos device contactsINTEL CORP·Filed 2021·Application pending·0 cites
- 3346US11101356B2Doped insulator cap to reduce source/drain diffusion for germanium NMOS transistorsINTEL CORP·Filed 2017·Granted Aug 24, 2021·0 cites·20 claims
- 3446US2021408239A1Plasma nitridation for gate oxide scaling of ge and sige transistorsINTEL CORP·Filed 2020·Application pending·0 cites
- 3545US2022190159A1Integrated circuit structures having gesnb source or drain structuresINTEL CORP·Filed 2020·Application pending·0 cites
- 3644US11575005B2Asymmetrical semiconductor nanowire field-effect transistorINTEL CORP·Filed 2018·Granted Feb 7, 2023·0 cites·17 claims
- 3744US2021408283A1Gate-all-around integrated circuit structures having strained source or drain structures on insulatorINTEL CORP·Filed 2020·Application pending·0 cites
- 3844US2021408284A1Gate-all-around integrated circuit structures having strained source or drain structures on gate dielectric layerINTEL CORP·Filed 2020·Application pending·0 cites
- 3943US2021407996A1Gate-all-around integrated circuit structures having strained dual nanoribbon channel structuresAGRAWAL ASHISH·Filed 2020·Application pending·0 cites
- 4040US2019348415A1Transistors employing cap layer for ge-rich source/drain regionsINTEL CORP·Filed 2017·Application pending·0 cites
- 4137US2019273133A1Transistor source/drain amorphous interlayer arrangementsINTEL CORP·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →