Inventor · disambiguated record
Simon H. Friedmann
Also filed as: FRIEDMANN SIMON · FRIEDMANN SIMON H · FRIEDMANN SIMON HERMANN
9 granted patents·1 pending application·2 citations·filing 2017–2024
78Inventor score
Technology areasG06F
Files withIBM10
Top patents by PatentIndex Score
10 records- 0176US10585797B2Operating different processor cache levelsIBM·Filed 2017·Granted Mar 10, 2020·1 cites·4 claims
- 0272US10169234B2Translation lookaside buffer purging with concurrent cache updatesIBM·Filed 2017·Granted Jan 1, 2019·1 cites·10 claims
- 0367US11182293B2Operating different processor cache levelsIBM·Filed 2019·Granted Nov 23, 2021·0 cites·19 claims
- 0461US10572384B2Operating different processor cache levelsIBM·Filed 2017·Granted Feb 25, 2020·0 cites·11 claims
- 0561US10268582B2Operating different processor cache levelsIBM·Filed 2018·Granted Apr 23, 2019·0 cites·1 claims
- 0656US10592414B2Filtering of redundantly scheduled write passesIBM·Filed 2017·Granted Mar 17, 2020·0 cites·18 claims
- 0755US11775444B1Fetch request arbiterIBM·Filed 2022·Granted Oct 3, 2023·0 cites·17 claims
- 0854US10169233B2Translation lookaside buffer purging with concurrent cache updatesIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 0954US10089231B1Filtering of redundently scheduled write passesIBM·Filed 2017·Granted Oct 2, 2018·0 cites·1 claims
- 1053US2025390433A1Coherent communication between a processor core and an acceleratorIBM·Filed 2024·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Simon H. Friedmann files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →