Inventor · disambiguated record
Siegmar Koeppe
Also filed as: KOEPPE SIEGMAR
15 granted patents·2 pending applications·152 citations·filing 1987–2012
92Inventor score
Top patents by PatentIndex Score
17 records- 0193US7492187B2Circuit arrangement for supplying configuration data in FPGA devicesINFINEON TECHNOLOGIES AG·Filed 2006·Granted Feb 17, 2009·28 cites·23 claims
- 0285US8854866B2Identification circuit and method for generating an identification bitHUBER PETER·Filed 2011·Granted Oct 7, 2014·12 cites·15 claims
- 0377US4799096AMonolithic integrated circuit comprising circuit branches parallel to one anotherSIEMENS AG·Filed 1987·Granted Jan 17, 1989·49 cites·5 claims
- 0466US7656204B2Divider circuitINFINEON TECHNOLOGIES AG·Filed 2007·Granted Feb 2, 2010·5 cites·14 claims
- 0564US8243555B2Apparatus and system with a time delay path and method for propagating a timing eventHENZLER STEPHAN·Filed 2008·Granted Aug 14, 2012·4 cites·22 claims
- 0663US8605526B2Memory reliability verification techniquesHUBER PETER·Filed 2011·Granted Dec 10, 2013·3 cites·20 claims
- 0759US8209523B2Data moving processorNORDQVIST ULF·Filed 2009·Granted Jun 26, 2012·3 cites·30 claims
- 0857US8223573B2Method and device for controlling a memory access and correspondingly configured semiconductor memoryKOEPPE SIEGMAR·Filed 2009·Granted Jul 17, 2012·4 cites·6 claims
- 0956US8331163B2Latch based memory deviceKOEPPE SIEGMAR·Filed 2010·Granted Dec 11, 2012·2 cites·32 claims
- 1053US8780648B2Latch based memory deviceINFINEON TECHNOLOGIES AG·Filed 2012·Granted Jul 15, 2014·1 cites·19 claims
- 1152US4852093AMethod for simulating a fault in a logic circuit and a simulation model for the implementation of the methodSIEMENS AG·Filed 1987·Granted Jul 25, 1989·20 cites·10 claims
- 1251US7177385B2Shift register for safely providing a configuration bitINFINEON TECHNOLOGIES AG·Filed 2004·Granted Feb 13, 2007·7 cites·28 claims
- 1345US4868825AMethod for simulating an open fault in a logic circuit comprising field effect transistors and simulation models for implementing the methodSIEMENS AG·Filed 1987·Granted Sep 19, 1989·14 cites·13 claims
- 1441US7439765B2Mask-programmable logic macro and method for programming a logic macroINFINEON TECHNOLOGIES AG·Filed 2006·Granted Oct 21, 2008·0 cites·20 claims
- 1539US2006294178A1Carry-ripple adderBERNHARDT MARC·Filed 2005·Application pending·0 cites
- 1630US5610531ATesting method for semiconductor circuit levelsSIEMENS AG·Filed 1995·Granted Mar 11, 1997·0 cites·13 claims
- 1728US2008079460A1Programmable logic cell, configurable cell, configurable cell arrangement, configurable logic array, mask programmable basic cell, mask programmable gate array and methodINFINEON TECHNOLOGIES AG·Filed 2006·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Siegmar Koeppe files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →