Inventor · disambiguated record
Siva Srinivas Kothamasu
Also filed as: KOTHAMASU SIVA · KOTHAMASU SIVA SRINIVAS
12 granted patents·4 pending applications·14 citations·filing 2014–2025
86Inventor score
Files withTEXAS INSTRUMENTS INC16
Top patents by PatentIndex Score
16 records- 0190US12141030B2Accessing error statistics from DRAM memories having integrated error correctionTEXAS INSTRUMENTS INC·Filed 2023·Granted Nov 12, 2024·1 cites·22 claims
- 0288US11714713B2Accessing error statistics from dram memories having integrated error correctionTEXAS INSTRUMENTS INC·Filed 2022·Granted Aug 1, 2023·1 cites·20 claims
- 0386US12132386B2Integrated circuit with low power mode managementTEXAS INSTRUMENTS INC·Filed 2023·Granted Oct 29, 2024·1 cites·20 claims
- 0480US2025068516A1Accessing error statistics from a circuit having integrated error correctionTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 0577US11403171B2Accessing error statistics from DRAM memories having integrated error correctionTEXAS INSTRUMENTS INC·Filed 2020·Granted Aug 2, 2022·1 cites·20 claims
- 0676US12271289B2System on a chip with an integrated configurable safety master microcontroller unitTEXAS INSTRUMENTS INC·Filed 2024·Granted Apr 8, 2025·0 cites·20 claims
- 0776US2025015698A1Integrated circuit with low power mode managementTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 0874US9627035B2Fail-safe I/O to achieve ultra low system powerTEXAS INSTRUMENTS INC·Filed 2016·Granted Apr 18, 2017·3 cites·20 claims
- 0971US2025199941A1System on a chip with an integrated configurable safety master microcontroller unitTEXAS INSTRUMENTS INC·Filed 2025·Application pending·0 cites
- 1070US9471140B2Valid context status retention in processor power mode managementTEXAS INSTRUMENTS INC·Filed 2014·Granted Oct 18, 2016·4 cites·20 claims
- 1168US11899563B2System on a chip with an integrated configurable safety master microcontroller unitTEXAS INSTRUMENTS INC·Filed 2022·Granted Feb 13, 2024·0 cites·20 claims
- 1265US10572344B2Accessing error statistics from DRAM memories having integrated error correctionTEXAS INSTRUMENTS INC·Filed 2018·Granted Feb 25, 2020·1 cites·16 claims
- 1363US10387690B2Integrated power supply scheme for powering memory card host interfaceTEXAS INSTRUMENTS INC·Filed 2017·Granted Aug 20, 2019·2 cites·19 claims
- 1457US12493340B2Power-on-reset signal isolation during lower power modeTEXAS INSTRUMENTS INC·Filed 2022·Granted Dec 9, 2025·0 cites·20 claims
- 1552US10262722B2Fail-safe input/output (IO) circuitTEXAS INSTRUMENTS INC·Filed 2017·Granted Apr 16, 2019·0 cites·21 claims
- 1649US2016035412A1Fail-safe i/o to achieve ultra low system powerTEXAS INSTRUMENTS INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →