Inventor · disambiguated record
Siddharth Rajan
Also filed as: RAJAN SIDDHARTH
13 granted patents·6 pending applications·142 citations·filing 2005–2024
89Inventor score
Files withOHIO STATE INNOVATION FOUNDATION11UNIV CALIFORNIA3TILAK VINAYAK2GEN ELECTRIC1MYERS ROBERTO C1
Top patents by PatentIndex Score
19 records- 0196US7948011B2N-polar aluminum gallium nitride/gallium nitride enhancement-mode field effect transistorUNIV CALIFORNIA·Filed 2006·Granted May 24, 2011·81 cites·37 claims
- 0291US7935985B2N-face high electron mobility transistors with low buffer leakage and low parasitic resistanceUNIV CALIFONIA·Filed 2008·Granted May 3, 2011·30 cites·18 claims
- 0390US11211525B2Tunnel junction ultraviolet light emitting diodes with enhanced light extraction efficiencyOHIO STATE INNOVATION FOUNDATION·Filed 2018·Granted Dec 28, 2021·15 cites·8 claims
- 0489US11658267B2Tunnel junction ultraviolet light emitting diodes with enhanced light extraction efficiencyOHIO STATE INNOVATION FOUNDATION·Filed 2021·Granted May 23, 2023·2 cites·19 claims
- 0583US7525130B2Polarization-doped field effect transistors (POLFETS) and materials and methods for making the sameUNIV CALIFORNIA·Filed 2005·Granted Apr 28, 2009·11 cites·28 claims
- 0661US2025087479A1Etching methods and patterned substrates made using said methodsOHIO STATE INNOVATION FOUNDATION·Filed 2024·Application pending·0 cites
- 0760US9478699B2Nanoscale emitters with polarization gradingMYERS ROBERTO C·Filed 2011·Granted Oct 25, 2016·2 cites·21 claims
- 0852US8159002B2Heterostructure device and associated methodTILAK VINAYAK·Filed 2007·Granted Apr 17, 2012·1 cites·17 claims
- 0950US11848389B2Low turn on and high breakdown voltage lateral diodeOHIO STATE INNOVATION FOUNDATION·Filed 2021·Granted Dec 19, 2023·0 cites·18 claims
- 1049US2024249954A1IN SITU DAMAGE FREE ETCHING OF Ga2O3 USING Ga FLUX FOR FABRICATING HIGH ASPECT RATIO 3D STRUCTURESOHIO STATE INNOVATION FOUNDATION·Filed 2022·Application pending·0 cites
- 1146US2009085065A1Method to fabricate iii-n semiconductor devices on the n-face of layers which are grown in the iii-face direction using wafer bonding and substrate removalUNIV CALIFORNIA·Filed 2008·Application pending·0 cites
- 1245US11848359B2Method of forming lateral pn junctions in III-nitrides using p-type and n-type co-doping and selective p-type activation and deactivationOHIO STATE INNOVATION FOUNDATION·Filed 2021·Granted Dec 19, 2023·0 cites·13 claims
- 1344US12490493B2Semiconductor devices with a compositionally graded layer, and methods of making and use thereofOHIO STATE INNOVATION FOUNDATION·Filed 2023·Granted Dec 2, 2025·0 cites·19 claims
- 1443US11476340B2Dielectric heterojunction deviceOHIO STATE INNOVATION FOUNDATION·Filed 2020·Granted Oct 18, 2022·0 cites·11 claims
- 1541US8697506B2Heterostructure device and associated methodTILAK VINAYAK·Filed 2012·Granted Apr 15, 2014·0 cites·9 claims
- 1639US11081555B2Electronic devices with ultra-high dielectric constant passivation and high mobility materialsOHIO STATE INNOVATION FOUNDATION·Filed 2019·Granted Aug 3, 2021·0 cites·9 claims
- 1739US2009140293A1Heterostructure device and associated methodGEN ELECTRIC·Filed 2007·Application pending·0 cites
- 1832US2018076354A1Ultraviolet light emitting diodes with tunnel junctionOHIO STATE INNOVATION FOUNDATION·Filed 2016·Application pending·0 cites
- 1925US2017033187A1Enhancement mode field effect transistor with doped buffer and drain field plateOHIO STATE INNOVATION FOUNDATION·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →