Inventor · disambiguated record
Sivanand Simanapalli
Also filed as: SIMANAPALLI SIVANAND
12 granted patents·760 citations·filing 1997–1998
93Inventor score
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12 records- 0196US5991785ADetermining an extremum value and its index in an array using a dual-accumulation processorLUCENT TECHNOLOGIES INC·Filed 1997·Granted Nov 23, 1999·490 cites·16 claims
- 0277US6029267ASingle-cycle, soft decision, compare-select operation using dual-add processorLUCENT TECHNOLOGIES INC·Filed 1997·Granted Feb 22, 2000·42 cites·15 claims
- 0374US6081921ABit insertion approach to convolutional encodingLUCENT TECHNOLOGIES INC·Filed 1997·Granted Jun 27, 2000·36 cites·10 claims
- 0465US5987490AMac processor with efficient Viterbi ACS operation and automatic traceback storeLUCENT TECHNOLOGIES INC·Filed 1997·Granted Nov 16, 1999·48 cites·17 claims
- 0559US6446193B1Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architectureAGERE SYST GUARDIAN CORP·Filed 1997·Granted Sep 3, 2002·35 cites·24 claims
- 0655US6530014B2Near-orthogonal dual-MAC instruction set architecture with minimal encoding bitsAGERE SYSTEMS INC·Filed 1998·Granted Mar 4, 2003·30 cites·14 claims
- 0753US5912908AMethod of efficient branch metric computation for a Viterbi convolutional decoderLUCENT TECHNOLOGIES INC·Filed 1997·Granted Jun 15, 1999·33 cites·12 claims
- 0850US6272188B1Single-cycle accelerator for extremun state searchAGERE SYST GUARDIAN CORP·Filed 1998·Granted Aug 7, 2001·14 cites·24 claims
- 0944US6009128AMetric acceleration on dual MAC processorLUCENT TECHNOLOGIES INC·Filed 1997·Granted Dec 28, 1999·10 cites·13 claims
- 1043US6002726AFM discriminator with automatic gain control for digital signal processorsLUCENT TECHNOLOGIES INC·Filed 1997·Granted Dec 14, 1999·9 cites·15 claims
- 1137US6064714AShifter capable of split operationLUCENT TECHNOLOGIES INC·Filed 1998·Granted May 16, 2000·5 cites·30 claims
- 1234US6801995B1Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codesAGERE SYSTEMS INC·Filed 1998·Granted Oct 5, 2004·8 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →