Inventor · disambiguated record
Sneha Bhalchandra Date
Also filed as: DATE SNEHA · DATE SNEHA BHALCHANDRA
10 granted patents·2 pending applications·69 citations·filing 2014–2024
86Inventor score
Top patents by PatentIndex Score
12 records- 0196US11336287B1Data processing engine array architecture with memory tilesXILINX INC·Filed 2021·Granted May 17, 2022·26 cites·20 claims
- 0295US11669464B1Multi-addressing mode for DMA and non-sequential read and write patternsXILINX INC·Filed 2020·Granted Jun 6, 2023·9 cites·20 claims
- 0394US10824584B1Device with data processing engine array that enables partial reconfigurationXILINX INC·Filed 2018·Granted Nov 3, 2020·13 cites·20 claims
- 0493US8965942B1Systems and methods for sample rate trackingROSSUM DAVID P·Filed 2014·Granted Feb 24, 2015·19 cites·20 claims
- 0579US2024256482A1Device with data processing engine array that enables partial reconfigurationXILINX INC·Filed 2024·Application pending·0 cites
- 0677US12105667B2Device with data processing engine array that enables partial reconfigurationXILINX INC·Filed 2023·Granted Oct 1, 2024·0 cites·20 claims
- 0776US11443091B1Data processing engines with cascade connected coresXILINX INC·Filed 2020·Granted Sep 13, 2022·1 cites·20 claims
- 0871US11372803B2Data processing engine tile architecture for an integrated circuitXILINX INC·Filed 2018·Granted Jun 28, 2022·1 cites·19 claims
- 0968US11599498B1Device with data processing engine array that enables partial reconfigurationXILINX INC·Filed 2020·Granted Mar 7, 2023·0 cites·20 claims
- 1063US12505068B2Tiled compute and programmable logic arrayXILINX INC·Filed 2023·Granted Dec 23, 2025·0 cites·18 claims
- 1157US2025370949A1Decoupling processing and interface clocks in an ipuXILINX INC·Filed 2024·Application pending·0 cites
- 1255US10623222B2Vectorized peak detection for signal processingXILINX INC·Filed 2018·Granted Apr 14, 2020·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →