Inventor · disambiguated record
Somasundaram Arunachalam
Also filed as: ARUNACHALAM SOMASUNDARAM
8 granted patents·3 pending applications·0 citations·filing 2019–2024
70Inventor score
Top patents by PatentIndex Score
11 records- 0163US12086600B2Branch target buffer with shared target bitsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Sep 10, 2024·0 cites·18 claims
- 0260US12260220B2Accelerating fetch target queue (FTQ) processing in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Mar 25, 2025·0 cites·20 claims
- 0356US12111757B2Fluid memory for high performance computing applicationsHEWLETT PACKARD ENTPR DEV LP·Filed 2022·Granted Oct 8, 2024·0 cites·18 claims
- 0453US12265501B1Planar file system for organizing and interrelating large data setsHEWLETT PACKARD ENTPR DEV LP·Filed 2024·Granted Apr 1, 2025·0 cites·19 claims
- 0550US11934840B2Classification of hardware componentsHEWLETT PACKARD ENTPR DEV LP·Filed 2021·Granted Mar 19, 2024·0 cites·20 claims
- 0649US12026091B2Orthogonal memory lane-based memory managementHEWLETT PACKARD ENTPR DEV LP·Filed 2021·Granted Jul 2, 2024·0 cites·20 claims
- 0749US2024192957A1Branch target buffer access systems and methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Application pending·0 cites
- 0849US2025045132A1Prioritized Message Access Lists for Inter-Process CommunicationHEWLETT PACKARD ENTPR DEV LP·Filed 2023·Application pending·0 cites
- 0945US12299482B2Cascaded priority mappingHEWLETT PACKARD ENTPR DEV LP·Filed 2021·Granted May 13, 2025·0 cites·20 claims
- 1043US11099958B2Instruction generation for validation of processor functionalityHEWLETT PACKARD ENTPR DEV LP·Filed 2019·Granted Aug 24, 2021·0 cites·20 claims
- 1143US2023342186A1Priority-based directed acyclic graph schedulingHEWLETT PACKARD ENTPR DEV LP·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →