Inventor · disambiguated record
Sotirios Athanasiou
Also filed as: ATHANASIOU SOTIRIOS
11 granted patents·1 pending application·20 citations·filing 2015–2024
84Inventor score
Files withST MICROELECTRONICS SA8ATHANASIOU SOTIRIOS2COMMISSARIAT ENERGIE ATOMIQUE1X FAB FRANCE SAS1
Top patents by PatentIndex Score
12 records- 0189US9831288B2Integrated circuit cointegrating a FET transistor and a RRAM memory pointCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2016·Granted Nov 28, 2017·7 cites·13 claims
- 0286US9837413B2Substrate contact land for an MOS transistor in an SOI substrate, in particular an FDSOI substrateST MICROELECTRONICS SA·Filed 2016·Granted Dec 5, 2017·5 cites·24 claims
- 0385US10367068B2Transistor structureST MICROELECTRONICS SA·Filed 2017·Granted Jul 30, 2019·4 cites·22 claims
- 0478US10096708B2Enhanced substrate contact for MOS transistor in an SOI substrate, in particular an FDSOI substrateST MICROELECTRONICS SA·Filed 2016·Granted Oct 9, 2018·3 cites·17 claims
- 0570US9947650B1Device for protection against electrostatic discharges with a distributed trigger circuitST MICROELECTRONICS SA·Filed 2017·Granted Apr 17, 2018·1 cites·16 claims
- 0659US2024417842A1In-situ steam generated oxynitrideATHANASIOU SOTIRIOS·Filed 2024·Application pending·0 cites
- 0757US11380766B2Transistor structureST MICROELECTRONICS SA·Filed 2019·Granted Jul 5, 2022·0 cites·15 claims
- 0855US10211201B2Device for protection against electrostatic discharges with a distributed trigger circuitST MICROELECTRONICS SA·Filed 2018·Granted Feb 19, 2019·0 cites·22 claims
- 0951US12116676B2In-situ steam generated oxynitrideATHANASIOU SOTIRIOS·Filed 2021·Granted Oct 15, 2024·0 cites·17 claims
- 1051US10128242B2Substrate contact land for an MOS transistor in an SOI substrate, in particular an FDSOI substrateST MICROELECTRONICS SA·Filed 2017·Granted Nov 13, 2018·0 cites·14 claims
- 1145US9746863B2Electronic device for heating an integrated structure, for example an MOS transistorST MICROELECTRONICS SA·Filed 2015·Granted Aug 29, 2017·0 cites·23 claims
- 1237US11973130B2Method of forming asymmetric differential spacers for optimized MOSFET performance and optimized MOSFET and SONOS co-integrationX FAB FRANCE SAS·Filed 2021·Granted Apr 30, 2024·0 cites·28 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →