Inventor · disambiguated record
Sohrab Kianian
Also filed as: KIANIAN SOHRAB
18 granted patents·2 pending applications·409 citations·filing 1998–2009
95Inventor score
Top patents by PatentIndex Score
20 records- 0194US6952034B2Semiconductor memory array of floating gate memory cells with buried source line and floating gateSILICON STORAGE TECH INC·Filed 2003·Granted Oct 4, 2005·64 cites·22 claims
- 0292US7533063B2Smart memory card walletSILICON STORAGE TECH INC·Filed 2001·Granted May 12, 2009·90 cites·28 claims
- 0391US7307308B2Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formationSILICON STORAGE TECH INC·Filed 2004·Granted Dec 11, 2007·61 cites·20 claims
- 0486US6861315B1Method of manufacturing an array of bi-directional nonvolatile memory cellsSILICON STORAGE TECH INC·Filed 2003·Granted Mar 1, 2005·31 cites·6 claims
- 0585US6891220B2Method of programming electrons onto a floating gate of a non-volatile memory cellSILICON STORAGE TECH INC·Filed 2004·Granted May 10, 2005·30 cites·5 claims
- 0680US7074672B2Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistorSILICON STORAGE TECH INC·Filed 2004·Granted Jul 11, 2006·23 cites·22 claims
- 0777US7190018B2Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formationSILICON STORAGE TECH INC·Filed 2003·Granted Mar 13, 2007·22 cites·8 claims
- 0875US6952033B2Semiconductor memory array of floating gate memory cells with buried bit-line and raised source lineSILICON STORAGE TECH INC·Filed 2002·Granted Oct 4, 2005·17 cites·51 claims
- 0972US7326614B2Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made therebySILICON STORAGE TECH INC·Filed 2004·Granted Feb 5, 2008·15 cites·36 claims
- 1071US6917069B2Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistorSILICON STORAGE TECH INC·Filed 2001·Granted Jul 12, 2005·14 cites·45 claims
- 1166US7537996B2Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gateSILICON STORAGE TECH INC·Filed 2005·Granted May 26, 2009·2 cites·19 claims
- 1265US6940125B2Vertical NROM and methods for making thereofSILICON STORAGE TECH INC·Filed 2003·Granted Sep 6, 2005·11 cites·23 claims
- 1363US7547603B2Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making sameSILICON STORAGE TECH INC·Filed 2006·Granted Jun 16, 2009·2 cites·11 claims
- 1462US7411246B2Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made therebySILICON STORAGE TECH INC·Filed 2003·Granted Aug 12, 2008·9 cites·25 claims
- 1559US7129536B2Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making sameSILICON STORAGE TECH INC·Filed 2004·Granted Oct 31, 2006·7 cites·24 claims
- 1652US7144778B2Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source lineSILICON STORAGE TECH INC·Filed 2004·Granted Dec 5, 2006·4 cites·24 claims
- 1749US2011034008A1Method for forming a textured surface on a semiconductor substrate using a nanofabric layerNANTERO INC·Filed 2009·Application pending·0 cites
- 1840US7205198B2Method of making a bi-directional read/program non-volatile floating gate memory cellSILICON STORAGE TECH INC·Filed 2006·Granted Apr 17, 2007·0 cites·9 claims
- 1940US5852577AElectrically erasable and programmable read-only memory having a small unit for program and eraseSILICON STORAGE TECH INC·Filed 1998·Granted Dec 22, 1998·7 cites·14 claims
- 2036US2007215931A1Non-volatile memory cell in a trench having a first portion deeper than a second portion, an array of such memory cells, and method of manufacturingKIANIAN SOHRAB·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →