Inventor · disambiguated record
Soummya Mallick
Also filed as: MALLICK SOUMMYA
44 granted patents·4 pending applications·2,061 citations·filing 1995–2006
99Inventor score
Top patents by PatentIndex Score
48 records- 0191US6212542B1Method and system for executing a program within a multiscalar processor by processing linked thread descriptorsIBM·Filed 1996·Granted Apr 3, 2001·228 cites·17 claims
- 0290US5913925AMethod and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-orderIBM·Filed 1996·Granted Jun 22, 1999·175 cites·22 claims
- 0389US5764969AMethod and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronizationIBM·Filed 1995·Granted Jun 9, 1998·168 cites·12 claims
- 0484US5887166AMethod and system for constructing a program including a navigation instructionIBM·Filed 1996·Granted Mar 23, 1999·124 cites·23 claims
- 0583US5802386ALatency-based scheduling of instructions in a superscalar processorIBM·Filed 1996·Granted Sep 1, 1998·114 cites·20 claims
- 0681US5961639AProcessor and method for dynamically inserting auxiliary instructions within an instruction stream during executionIBM·Filed 1996·Granted Oct 5, 1999·106 cites·16 claims
- 0780US5953520AAddress translation buffer for data processing system emulation modeIBM·Filed 1997·Granted Sep 14, 1999·88 cites·16 claims
- 0880US5802572AWrite-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cacheIBM·Filed 1996·Granted Sep 1, 1998·90 cites·19 claims
- 0976US5870575AIndirect unconditional branches in data processing system emulation modeIBM·Filed 1997·Granted Feb 9, 1999·74 cites·10 claims
- 1075US5870616ASystem and method for reducing power consumption in an electronic circuitIBM·Filed 1996·Granted Feb 9, 1999·68 cites·22 claims
- 1172US5752014AAutomatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch predictionIBM·Filed 1996·Granted May 12, 1998·60 cites·21 claims
- 1268US5956495AMethod and system for processing branch instructions during emulation in a data processing systemIBM·Filed 1997·Granted Sep 21, 1999·53 cites·10 claims
- 1368US5897655ASystem and method for cache replacement within a cache set based on valid, modified or least recently used status in order of preferenceIBM·Filed 1996·Granted Apr 27, 1999·50 cites·10 claims
- 1467US5805907ASystem and method for reducing power consumption in an electronic circuitIBM·Filed 1996·Granted Sep 8, 1998·48 cites·12 claims
- 1564US5995743AMethod and system for interrupt handling during emulation in a data processing systemIBM·Filed 1997·Granted Nov 30, 1999·43 cites·8 claims
- 1663US5898864AMethod and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processorsIBM·Filed 1997·Granted Apr 27, 1999·42 cites·12 claims
- 1763US5611063AMethod for executing speculative load instructions in high-performance processorsIBM·Filed 1996·Granted Mar 11, 1997·44 cites·11 claims
- 1862US5913054AMethod and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycleIBM·Filed 1996·Granted Jun 15, 1999·45 cites·8 claims
- 1961US5694565AMethod and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructionsIBM·Filed 1995·Granted Dec 2, 1997·34 cites·4 claims
- 2059US5867684AMethod and processor that permit concurrent execution of a store multiple instruction and a dependent instructionIBM·Filed 1997·Granted Feb 2, 1999·30 cites·2 claims
- 2158US5812823AMethod and system for performing an emulation context save and restore that is transparent to the operating systemIBM·Filed 1996·Granted Sep 22, 1998·36 cites·17 claims
- 2256US5802556AMethod and apparatus for correcting misaligned instruction dataIBM·Filed 1996·Granted Sep 1, 1998·30 cites·12 claims
- 2354US5619408AMethod and system for recoding noneffective instructions within a data processing systemIBM·Filed 1995·Granted Apr 8, 1997·24 cites·11 claims
- 2452US6061777AApparatus and method for reducing the number of rename registers required in the operation of a processorIBM·Filed 1997·Granted May 9, 2000·25 cites·28 claims
- 2552US5897666AGeneration of unique address alias for memory disambiguation buffer to avoid false collisionsIBM·Filed 1996·Granted Apr 27, 1999·26 cites·20 claims
- 2650US5872948AProcessor and method for out-of-order execution of instructions based upon an instruction parameterIBM·Filed 1996·Granted Feb 16, 1999·23 cites·24 claims
- 2749US5732235AMethod and system for minimizing the number of cycles required to execute semantic routinesIBM·Filed 1996·Granted Mar 24, 1998·22 cites·11 claims
- 2848US5765191AMethod for implementing a four-way least recently used (LRU) mechanism in high-performanceIBM·Filed 1996·Granted Jun 9, 1998·20 cites·8 claims
- 2948US5758140AMethod and system for emulating instructions by performing an operation directly using special-purpose register contentsIBM·Filed 1996·Granted May 26, 1998·19 cites·18 claims
- 3047US5802340AMethod and system of executing speculative store instructions in a parallel processing computer systemIBM·Filed 1995·Granted Sep 1, 1998·20 cites·10 claims
- 3146US2007168937A1Apparatus and method of application virtualizationMALLICK SOUMMYA·Filed 2006·Application pending·0 cites
- 3245US5812812AMethod and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issueIBM·Filed 1996·Granted Sep 22, 1998·19 cites·8 claims
- 3345US5787479AMethod and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operationIBM·Filed 1996·Granted Jul 28, 1998·17 cites·11 claims
- 3444US5897654AMethod and system for efficiently fetching from cache during a cache fill operationIBM·Filed 1997·Granted Apr 27, 1999·16 cites·12 claims
- 3542US2007094439A1Expandable portable solid-state device & methodXIPKEY INC·Filed 2005·Application pending·0 cites
- 3641US2006294356A1Apparatus and method of an executable-in-place flash deviceXIPKEY INC·Filed 2005·Application pending·0 cites
- 3740US2005080761A1Data path media security system and method in a storage area networkNEOSCALE SYSTEMS·Filed 2003·Application pending·0 cites
- 3839US5754811AInstruction dispatch queue for improved instruction cache to queue timingFiled 1996·Granted May 19, 1998·11 cites·18 claims
- 3938US5805916AMethod and apparatus for dynamic allocation of registers for intermediate floating-point resultsIBM·Filed 1996·Granted Sep 8, 1998·10 cites·13 claims
- 4036US5809323AMethod and apparatus for executing fixed-point instructions within idle execution units of a superscalar processorIBM·Filed 1995·Granted Sep 15, 1998·9 cites·13 claims
- 4136US5717587AMethod and system for recording noneffective instructions within a data processing systemIBM·Filed 1996·Granted Feb 10, 1998·7 cites·11 claims
- 4236US5664120AMethod for executing instructions and execution unit instruction reservation table within an in-order completion processorIBM·Filed 1995·Granted Sep 2, 1997·8 cites·12 claims
- 4335US5765215AMethod and system for efficient rename buffer deallocation within a processorIBM·Filed 1995·Granted Jun 9, 1998·8 cites·12 claims
- 4434US5870577ASystem and method for dispatching two instructions to the same execution unit in a single cycleIBM·Filed 1996·Granted Feb 9, 1999·7 cites·20 claims
- 4534US5758117AMethod and system for efficiently utilizing rename buffers to reduce dispatch unit stalls in a superscalar processorIBM·Filed 1995·Granted May 26, 1998·5 cites·10 claims
- 4634US5758141AMethod and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state registerIBM·Filed 1995·Granted May 26, 1998·7 cites·8 claims
- 4733US5850563AProcessor and method for out-of-order completion of floating-point operations during load/store multiple operationsIBM·Filed 1995·Granted Dec 15, 1998·5 cites·4 claims
- 4831US5764940AProcessor and method for executing a branch instruction and an associated target instruction utilizing a single instruction fetchIBM·Filed 1996·Granted Jun 9, 1998·3 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →