Inventor · disambiguated record
Somnath Paul
Also filed as: PAUL SOMNATH
45 granted patents·10 pending applications·426 citations·filing 2000–2023
98Inventor score
Top patents by PatentIndex Score
55 records- 0196US9734880B1Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctionsINTEL CORP·Filed 2016·Granted Aug 15, 2017·33 cites·8 claims
- 0286US10665222B2Method and system of temporal-domain feature extraction for automatic speech recognitionINTEL CORP·Filed 2018·Granted May 26, 2020·7 cites·19 claims
- 0384US9953690B2Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctionsINTEL CORP·Filed 2017·Granted Apr 24, 2018·5 cites·15 claims
- 0482US10878313B2Post synaptic potential-based learning ruleINTEL CORP·Filed 2017·Granted Dec 29, 2020·5 cites·19 claims
- 0581US10129219B1Methods and systems for securing data stored at a storage area networkQLOGIC CORP·Filed 2016·Granted Nov 13, 2018·5 cites·20 claims
- 0680US7272675B1First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit accessCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted Sep 18, 2007·33 cites·18 claims
- 0779US6816955B1Logic for providing arbitration for synchronous dual-port memoryCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Nov 9, 2004·28 cites·23 claims
- 0877US7036037B1Multi-bit deskewing of bus signals using a training patternCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Apr 25, 2006·25 cites·20 claims
- 0976US8094562B1Transmission of a continuous datastream through a re-clocked frame-based transport networkBAUMBACH JASON·Filed 2005·Granted Jan 10, 2012·10 cites·13 claims
- 1076US7379467B1Scheduling store-forwarding of back-to-back multi-channel packet fragmentsCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted May 27, 2008·25 cites·21 claims
- 1175US10586147B2Neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a neuromorphic computing environmentINTEL CORP·Filed 2016·Granted Mar 10, 2020·3 cites·21 claims
- 1275US7496109B1Method of maximizing bandwidth efficiency in a protocol processorCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted Feb 24, 2009·22 cites·26 claims
- 1375US7016349B1Logic for generating multicast/unicast address (es)CYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Mar 21, 2006·21 cites·19 claims
- 1475US6957309B1Method and apparatus for re-accessing a FIFO locationCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Oct 18, 2005·22 cites·21 claims
- 1573US6760872B2Configurable and memory architecture independent memory built-in self testCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Jul 6, 2004·20 cites·28 claims
- 1673US6704863B1Low-latency DMA handling in pipelined processorsCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Mar 9, 2004·18 cites·21 claims
- 1771US6721878B1Low-latency interrupt handling during memory access delay periods in microprocessorsCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Apr 13, 2004·16 cites·17 claims
- 1870US10403266B2Detecting keywords in audio using a spiking neural networkINTEL CORP·Filed 2017·Granted Sep 3, 2019·2 cites·22 claims
- 1970US6816979B1Configurable fast clock detection logic with programmable resolutionCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Nov 9, 2004·19 cites·17 claims
- 2070US6631455B1Logic for initializing the depth of the queue pointer memoryCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Oct 7, 2003·14 cites·20 claims
- 2169US10892012B2Apparatus, video processing unit and method for clustering events in a content addressable memoryINTEL CORP·Filed 2018·Granted Jan 12, 2021·2 cites·25 claims
- 2268US6925506B1Architecture for implementing virtual multiqueue fifosCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Aug 2, 2005·13 cites·20 claims
- 2367US6578118B1Method and logic for storing and extracting in-band multicast port information stored along with the data in a single memory without memory read cycle overheadCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Jun 10, 2003·12 cites·20 claims
- 2465US10635968B2Technologies for memory management of neural networks with sparse connectivityINTEL CORP·Filed 2016·Granted Apr 28, 2020·1 cites·21 claims
- 2563US11176994B2Techniques for multi-read and multi-write of memory circuitINTEL CORP·Filed 2020·Granted Nov 16, 2021·0 cites·25 claims
- 2663US10755771B2Techniques for multi-read and multi-write of memory circuitINTEL CORP·Filed 2018·Granted Aug 25, 2020·1 cites·22 claims
- 2763US6948030B1FIFO memory system and methodCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Sep 20, 2005·10 cites·16 claims
- 2862US7512075B1Method and apparatus for collecting statistical information from a plurality of packet processing blocksCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted Mar 31, 2009·7 cites·19 claims
- 2962US6810098B1FIFO read interface protocolCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Oct 26, 2004·8 cites·18 claims
- 3062US6715021B1Out-of-band look-ahead arbitration method and/or architectureCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Mar 30, 2004·8 cites·20 claims
- 3162US6629226B1Fifo read interface protocolCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Sep 30, 2003·8 cites·19 claims
- 3259US7073019B2Method and apparatus for assembling non-aligned packet fragments over multiple cyclesCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Jul 4, 2006·7 cites·9 claims
- 3358US7138930B1Multiple byte data path encoding/decoding device and methodCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted Nov 21, 2006·5 cites·18 claims
- 3458US2023273832A1Power management for execution of machine learning workloadsINTEL CORP·Filed 2023·Application pending·0 cites
- 3557US6625711B1Method and/or architecture for implementing queue expansion in multiqueue devicesCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Sep 23, 2003·5 cites·22 claims
- 3657US6581144B1Method and logic for initializing the forward-pointer memory during normal operation of the device as a background processCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Jun 17, 2003·5 cites·20 claims
- 3753US12197601B2Hardware offload circuitryINTEL CORP·Filed 2021·Granted Jan 14, 2025·0 cites·22 claims
- 3852US11513893B2Concurrent compute and ECC for in-memory matrix vector operationsINTEL CORP·Filed 2020·Granted Nov 29, 2022·0 cites·21 claims
- 3951US11450672B2Ultra-deep compute static random access memory with high compute throughput and multi-directional data propagationINTEL CORP·Filed 2020·Granted Sep 20, 2022·0 cites·18 claims
- 4050US9337952B2Embedded resilient bufferPAUL SOMNATH·Filed 2013·Granted May 10, 2016·1 cites·12 claims
- 4149US10489702B2Hybrid compression scheme for efficient storage of synaptic weights in hardware neuromorphic coresINTEL CORP·Filed 2016·Granted Nov 26, 2019·0 cites·24 claims
- 4249US2020133884A1Nvram system memory with memory side cache that favors written to items and/or includes regions with customized temperature induced speed settingsINTEL CORP·Filed 2019·Application pending·0 cites
- 4347US8990662B2Techniques for resilient communicationINTEL CORP·Filed 2012·Granted Mar 24, 2015·0 cites·24 claims
- 4445US10748060B2Pre-synaptic learning using delayed causal updatesINTEL CORP·Filed 2016·Granted Aug 18, 2020·0 cites·23 claims
- 4545US2025156356A1Techniques to utilize near memory compute circuitry for memory-bound workloadsINTEL CORP·Filed 2022·Application pending·0 cites
- 4644US11908542B2Energy efficient memory array with optimized burst read and write data accessINTEL CORP·Filed 2019·Granted Feb 20, 2024·0 cites·20 claims
- 4744US2022415050A1Apparatus and method for increasing activation sparsity in visual media artificial intelligence (ai) applicationsINTEL CORP·Filed 2022·Application pending·0 cites
- 4844US2022012563A1Methods and apparatus for high throughput compression of neural network weightsCASTRO GONZALEZ ALEJANDRO·Filed 2021·Application pending·0 cites
- 4943US7356044B1Method and apparatus for the deletion of bytes when performing byte rate adaptationCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Apr 8, 2008·0 cites·27 claims
- 5042US2020183922A1Nearest neighbor search logic circuit with reduced latency and power consumptionINTEL CORP·Filed 2020·Application pending·0 cites
Showing the top 50 of 55 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →