Inventor · disambiguated record
Soh Yun Siah
Also filed as: SIAH SOH YUN
28 granted patents·6 pending applications·798 citations·filing 1998–2023
97Inventor score
Files withGLOBALFOUNDRIES SG PTE LTD16CHARTERED SEMICONDUCTOR MFG13TAN JUAN BOON3GLOBALFOUNDERIES SINGAPORE PTE LTD1LI LIANG1
Top patents by PatentIndex Score
34 records- 0198US9905282B1Top electrode dome formationGLOBALFOUNDRIES SG PTE LTD·Filed 2017·Granted Feb 27, 2018·15 cites·20 claims
- 0292US6228727B1Method to form shallow trench isolations with rounded corners and reduced trench oxide recessCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted May 8, 2001·142 cites·18 claims
- 0392US6153485ASalicide formation on narrow poly lines by pulling back of spacerCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Nov 28, 2000·108 cites·7 claims
- 0492US6025267ASilicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devicesCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Feb 15, 2000·140 cites·27 claims
- 0588US6350661B2Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contactsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Feb 26, 2002·49 cites·5 claims
- 0687US10608046B2Integrated two-terminal device with logic device for embedded applicationGLOBALFOUNDRIES SG PTE LTD·Filed 2019·Granted Mar 31, 2020·4 cites·16 claims
- 0787US6734082B2Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shapeCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted May 11, 2004·45 cites·28 claims
- 0884US10446607B2Integrated two-terminal device with logic device for embedded applicationGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted Oct 15, 2019·4 cites·14 claims
- 0984US6762085B2Method of forming a high performance and low cost CMOS deviceCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jul 13, 2004·36 cites·27 claims
- 1084US6265302B1Partially recessed shallow trench isolation method for fabricating borderless contactsCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jul 24, 2001·77 cites·17 claims
- 1182US6165871AMethod of making low-leakage architecture for sub-0.18 μm salicided CMOS deviceCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Dec 26, 2000·55 cites·26 claims
- 1281US8759947B2Back-side MOM/MIM devicesTAN JUAN BOON·Filed 2012·Granted Jun 24, 2014·8 cites·18 claims
- 1380US10062641B2Integrated circuits including a dummy metal feature and methods of forming the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted Aug 28, 2018·3 cites·16 claims
- 1475US9111866B2Method of forming split-gate cell for non-volative memory devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Aug 18, 2015·3 cites·5 claims
- 1575US6093628AUltra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS applicationCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Jul 25, 2000·41 cites·19 claims
- 1674US6271133B1Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabricationCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Aug 7, 2001·36 cites·6 claims
- 1771US8716856B2Device with integrated power supplyTAN JUAN BOON·Filed 2012·Granted May 6, 2014·3 cites·20 claims
- 1868US10439129B2Shielded MRAM cellGLOBALFOUNDRIES SG PTE LTD·Filed 2018·Granted Oct 8, 2019·1 cites·17 claims
- 1959US11158646B2Memory device with dielectric blocking layer for improving interpoly dielectric breakdownGLOBALFOUNDRIES SG PTE LTD·Filed 2019·Granted Oct 26, 2021·0 cites·20 claims
- 2059US2025142983A1Single-photon avalanche diodes with hybrid trench isolation structuresGLOBALFOUNDRIES SG PTE LTD·Filed 2023·Application pending·0 cites
- 2158US6297126B1Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contactsCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Oct 2, 2001·20 cites·11 claims
- 2257US8569173B2Methods of protecting elevated polysilicon structures during etching processesLI LIANG·Filed 2011·Granted Oct 29, 2013·1 cites·12 claims
- 2356US6586314B1Method of forming shallow trench isolation regions with improved corner roundingCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jul 1, 2003·7 cites·29 claims
- 2456US2024389467A1Magnetic-tunnel-junction devices for a magnetic-field sensorGLOBALFOUNDRIES SG PTE LTD·Filed 2023·Application pending·0 cites
- 2555US10224338B2Cost-effective method to form a reliable memory device with selective silicidation and resulting deviceGLOBALFOUNDRIES SG PTE LTD·Filed 2017·Granted Mar 5, 2019·0 cites·11 claims
- 2651US11119917B2Neuromorphic memories with split gate flash multi-level cell and method of making the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2018·Granted Sep 14, 2021·0 cites·18 claims
- 2749US8957523B2Dielectric posts in metal layersGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Feb 17, 2015·0 cites·20 claims
- 2846US9236391B2Method of forming split-gate cell for non-volative memory devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2015·Granted Jan 12, 2016·0 cites·5 claims
- 2943US2015061156A1Pad solutions for reliable bondsGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Application pending·0 cites
- 3038US2014264733A1Device with integrated passive componentGLOBALFOUNDERIES SINGAPORE PTE LTD·Filed 2013·Application pending·0 cites
- 3138US2004029321A1Method for forming gate insulating layer having multiple dielectric constants and multiple equivalent oxide thicknessesCHARTERED SEMICONDUCTOR MFG·Filed 2002·Application pending·0 cites
- 3237US9929165B1Method for producing integrated circuit memory cells with less dedicated lithographic stepsGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted Mar 27, 2018·0 cites·20 claims
- 3336US9793208B2Plasma discharge pathGLOBALFOUNDRIES SG PTE LTD·Filed 2015·Granted Oct 17, 2017·0 cites·20 claims
- 3435US2013277810A1Method for forming heat sink with through silicon viasTAN JUAN BOON·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →