Inventor · disambiguated record
Srinivasan Dasasathyan
Also filed as: DASASATHYAN SRINIVASAN
24 granted patents·3 pending applications·464 citations·filing 2002–2024
96Inventor score
Top patents by PatentIndex Score
27 records- 0196US6789244B1Placement of clock objects under constraintsXILINX INC·Filed 2002·Granted Sep 7, 2004·178 cites·20 claims
- 0293US7143380B1Method for application of network flow techniques under constraintsXILINX INC·Filed 2002·Granted Nov 28, 2006·97 cites·44 claims
- 0392US8418115B1Routability based placement for multi-die integrated circuitsTOM MARVIN·Filed 2010·Granted Apr 9, 2013·36 cites·20 claims
- 0488US11003826B1Automated analysis and optimization of circuit designsXILINX INC·Filed 2019·Granted May 11, 2021·16 cites·18 claims
- 0587US8473881B1Multi-resource aware partitioning for integrated circuitsFANG WEI MARK·Filed 2011·Granted Jun 25, 2013·20 cites·14 claims
- 0679US10867093B1System and method for an electronic design tool providing automated guidance and interface for circuit design processingXILINX INC·Filed 2019·Granted Dec 15, 2020·4 cites·19 claims
- 0778US8230377B1Control set constraint driven force directed analytical placer for programmable integrated circuitsFANG WEI MARK·Filed 2009·Granted Jul 24, 2012·12 cites·20 claims
- 0878US8091060B1Clock domain partitioning of programmable integrated circuitsTOM MARVIN·Filed 2009·Granted Jan 3, 2012·10 cites·12 claims
- 0976US11714950B2Automated timing closure on circuit designsXILINX INC·Filed 2021·Granted Aug 1, 2023·1 cites·20 claims
- 1076US8312405B1Method of placing input/output blocks on an integrated circuit deviceSLONIM VICTOR·Filed 2009·Granted Nov 13, 2012·11 cites·20 claims
- 1176US8225262B1Method of and system for placing clock circuits in an integrated circuitTOM MARVIN·Filed 2009·Granted Jul 17, 2012·10 cites·20 claims
- 1274US9501604B1Testing critical paths of a circuit designXILINX INC·Filed 2014·Granted Nov 22, 2016·5 cites·20 claims
- 1371US8448122B1Implementing sub-circuits with predictable behavior within a circuit designSUTHAR VISHAL·Filed 2009·Granted May 21, 2013·7 cites·18 claims
- 1471US7735039B1Methods of estimating net delays in tile-based PLD architecturesXILINX INC·Filed 2007·Granted Jun 8, 2010·6 cites·20 claims
- 1570US7636876B1Cost-based performance driven legalization technique for placement in logic designsXILINX INC·Filed 2006·Granted Dec 22, 2009·5 cites·20 claims
- 1670US6857115B1Placement of objects with partial shape restrictionXILINX INC·Filed 2002·Granted Feb 15, 2005·15 cites·26 claims
- 1767US7392499B1Placement of input/output blocks of an electronic design in an integrated circuitXILINX INC·Filed 2005·Granted Jun 24, 2008·4 cites·20 claims
- 1861US7149994B1Integrated clock and input output placerXILINX INC·Filed 2003·Granted Dec 12, 2006·8 cites·38 claims
- 1960US7313778B1Method system and apparatus for floorplanning programmable logic designsXILINX INC·Filed 2004·Granted Dec 25, 2007·8 cites·27 claims
- 2059US7149993B1Method, system, and apparatus for incremental design in programmable logic devices using floorplanningXILINX INC·Filed 2004·Granted Dec 12, 2006·7 cites·20 claims
- 2158US2025272599A1On-site updating of machine learning models and machine learning models incorporating hardware and runtime attributesXILINX INC·Filed 2024·Application pending·0 cites
- 2256US11586791B1Visualization of data buses in circuit designsXILINX INC·Filed 2021·Granted Feb 21, 2023·0 cites·20 claims
- 2353US12462082B2Satisfying circuit design constraints using a combination of machine learning modelsXILINX INC·Filed 2022·Granted Nov 4, 2025·0 cites·20 claims
- 2451US7240315B1Automated local clock placement for FPGA designsXILINX INC·Filed 2003·Granted Jul 3, 2007·4 cites·17 claims
- 2547US12019964B1Optimizing use of computer resources in implementing circuit designs through machine learningXILINX INC·Filed 2021·Granted Jun 25, 2024·0 cites·20 claims
- 2646US2024311541A1Pre-placement clocking identification and resolution for circuit designsXILINX INC·Filed 2023·Application pending·0 cites
- 2746US2024362393A1Prediction of routing congestionXILINX INC·Filed 2023·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →