Inventor · disambiguated record
Srinivasa Rao Kothamasu
Also filed as: KOTHAMASU SRINIVASA RAO
8 granted patents·5 pending applications·10 citations·filing 2010–2014
78Inventor score
Files withKOTHAMASU SRINIVASA RAO4LSI CORP2CHOUDHURY DEBJIT ROY1MEHTA ROMESHKUMAR BHARATKUMAR1NATION GEORGE WAYNE1
Top patents by PatentIndex Score
13 records- 0163US8504756B2System, circuit and method for improving system-on-chip bandwidth performance for high latency peripheral read accessesKOTHAMASU SRINIVASA RAO·Filed 2011·Granted Aug 6, 2013·4 cites·21 claims
- 0261US8527684B2Closed loop dynamic interconnect bus allocation method and architecture for a multi layer SoCKOTHAMASU SRINIVASA RAO·Filed 2010·Granted Sep 3, 2013·2 cites·16 claims
- 0351US8667196B2Interconnect congestion reduction for memory-mapped peripheralsKOTHAMASU SRINIVASA RAO·Filed 2012·Granted Mar 4, 2014·1 cites·21 claims
- 0448US8583844B2System and method for optimizing slave transaction ID width based on sparse connection in multilayer multilevel interconnect system-on-chip architecturePULLAGOUNDAPATTI SAKTHIVEL KOMARASAMY·Filed 2011·Granted Nov 12, 2013·1 cites·16 claims
- 0547US8923087B2Method and apparatus for decreasing leakage power consumption in power gated memoriesMEHTA ROMESHKUMAR BHARATKUMAR·Filed 2012·Granted Dec 30, 2014·2 cites·24 claims
- 0640US2015269054A1Multiple Core Execution Trace BufferLSI CORP·Filed 2014·Application pending·0 cites
- 0739US8924779B2Proxy responder for handling anomalies in a hardware systemNATION GEORGE WAYNE·Filed 2012·Granted Dec 30, 2014·0 cites·23 claims
- 0838US2013111181A1Methods and apparatus for increasing device access performance in data processing systemsKOTHAMASU SRINIVASA RAO·Filed 2011·Application pending·0 cites
- 0935US8904221B2Arbitration circuitry for asynchronous memory accessesPALANIAPPAN SATHAPPAN·Filed 2011·Granted Dec 2, 2014·0 cites·20 claims
- 1032US8533377B2System and method for allocating transaction ID in a system with a plurality of processing modulesVALLAPANENI VENKAT RAO·Filed 2011·Granted Sep 10, 2013·0 cites·18 claims
- 1132US2013314819A1Electronic Storage System ArchitectureCHOUDHURY DEBJIT ROY·Filed 2012·Application pending·0 cites
- 1229US2014025852A1Configurable Response Generator for Varied Regions of System Address SpaceRAMAKRISHNA SREENATH SHAMBU·Filed 2012·Application pending·0 cites
- 1326US2014115229A1Method and system to reduce system boot loader download time for spi based flash memoriesLSI CORP·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →