Inventor · disambiguated record
Sridhar Krishnamurthy
Also filed as: KRISHNAMURTHY SRIDHAR
31 granted patents·1 pending application·1,158 citations·filing 1996–2017
97Inventor score
Files withXILINX INC21TRISCEND CORP3JDS UNIPHASE CORP1KRISHNAMURTHY SRIDHAR1MUDAKARA GLOBAL SOLUTIONS1
Top patents by PatentIndex Score
32 records- 0197US5963050AConfigurable logic element with fast feedback pathsXILINX INC·Filed 1997·Granted Oct 5, 1999·129 cites·13 claims
- 0296US5936424AHigh speed bus with tree structure for selecting bus driverXILINX INC·Filed 1997·Granted Aug 10, 1999·128 cites·13 claims
- 0394US6467009B1Configurable processor system unitTRISCEND CORP·Filed 1998·Granted Oct 15, 2002·294 cites·109 claims
- 0493US5942913AFPGA repeatable interconnect structure with bidirectional and unidirectional interconnect linesXILINX INC·Filed 1997·Granted Aug 24, 1999·91 cites·9 claims
- 0591US10068048B1Generating clock trees for a circuit designXILINX INC·Filed 2016·Granted Sep 4, 2018·12 cites·18 claims
- 0686US10366201B1Timing closure of circuit designs for integrated circuitsXILINX INC·Filed 2017·Granted Jul 30, 2019·5 cites·20 claims
- 0786US6574655B1Associative management of multimedia assets and associated resources using multi-domain agent-based communication between heterogeneous peersTHOMSON LICENSING SA·Filed 1999·Granted Jun 3, 2003·281 cites·28 claims
- 0885US7478356B1Timing driven logic block configurationXILINX INC·Filed 2005·Granted Jan 13, 2009·16 cites·17 claims
- 0982US10042971B1Placement and routing of clock signals for a circuit designXILINX INC·Filed 2016·Granted Aug 7, 2018·5 cites·18 claims
- 1080US7926016B1Timing driven logic block configurationXILINX INC·Filed 2008·Granted Apr 12, 2011·10 cites·18 claims
- 1180US7610573B1Implementation of alternate solutions in technology mapping and placementXILINX INC·Filed 2007·Granted Oct 27, 2009·11 cites·12 claims
- 1280US7249335B1Methods of routing programmable logic devices to minimize programming timeXILINX INC·Filed 2006·Granted Jul 24, 2007·9 cites·8 claims
- 1378US8010923B1Latch based optimization during implementation of circuit designs for programmable logic devicesXILINX INC·Filed 2008·Granted Aug 30, 2011·7 cites·16 claims
- 1477US5847580AHigh speed bidirectional bus with multiplexersXILINX INC·Filed 1996·Granted Dec 8, 1998·32 cites·20 claims
- 1576US6754760B1Programmable interface for a configurable system busXILINX INC·Filed 2000·Granted Jun 22, 2004·24 cites·20 claims
- 1674US9330220B1Clock region partitioning and clock routingXILINX INC·Filed 2014·Granted May 3, 2016·4 cites·20 claims
- 1774US7111214B1Circuits and methods for testing programmable logic devices using lookup tables and carry chainsXILINX INC·Filed 2002·Granted Sep 19, 2006·20 cites·40 claims
- 1872US7784006B1Method and apparatus for directed physical implementation of a circuit design for an integrated circuitXILINX INC·Filed 2006·Granted Aug 24, 2010·7 cites·13 claims
- 1971US8448122B1Implementing sub-circuits with predictable behavior within a circuit designSUTHAR VISHAL·Filed 2009·Granted May 21, 2013·7 cites·18 claims
- 2071US7058919B1Methods of generating test designs for testing specific routing resources in programmable logic devicesXILINX INC·Filed 2003·Granted Jun 6, 2006·15 cites·33 claims
- 2167US6944809B2Methods of resource optimization in programmable logic devices to reduce test timeXILINX INC·Filed 2002·Granted Sep 13, 2005·13 cites·19 claims
- 2264US9298868B2Hierarchical pushdown of cells and nets to any logical depthNVIDIA CORP·Filed 2013·Granted Mar 29, 2016·2 cites·20 claims
- 2360US5844424AProgrammably bidirectional buffered interconnect circuitXILINX INC·Filed 1997·Granted Dec 1, 1998·16 cites·2 claims
- 2457US6658547B1Method and apparatus for specifying address offsets and alignment in logic designTRISCEND CORP·Filed 2000·Granted Dec 2, 2003·6 cites·38 claims
- 2556US7143384B1Methods of routing programmable logic devices to minimize programming timeXILINX INC·Filed 2003·Granted Nov 28, 2006·4 cites·24 claims
- 2654US9042431B1Wide band deterministic interfaceYADAVALLI VENKAT·Filed 2009·Granted May 26, 2015·3 cites·19 claims
- 2752US6661812B1Bidirectional bus for use as an interconnect routing resourceTRISCEND CORP·Filed 2000·Granted Dec 9, 2003·6 cites·18 claims
- 2850US8005886B2Systems and methods for generating network messagesJDS UNIPHASE CORP·Filed 2006·Granted Aug 23, 2011·1 cites·16 claims
- 2948US8146041B1Latch based optimization during implementation of circuit designs for programmable logic devicesSRINIVASAN SANKARANARAYANAN·Filed 2011·Granted Mar 27, 2012·0 cites·10 claims
- 3039US6910002B1Method and apparatus for specifying addressability and bus connections in a logic designXILINX INC·Filed 2000·Granted Jun 21, 2005·0 cites·29 claims
- 3130US2006149556A1Sequential-data correlation at real-time on multiple media and multiple data typesKRISHNAMURTHY SRIDHAR·Filed 2005·Application pending·0 cites
- 3226US6975990B2Sequential-data synchronization at real-time on an analog and a digital mediumMUDAKARA GLOBAL SOLUTIONS·Filed 2001·Granted Dec 13, 2005·0 cites·40 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →