Inventor · disambiguated record
Srinivas Perisetty
Also filed as: PERISETTY SRINIVAS
33 granted patents·2 pending applications·494 citations·filing 2004–2021
97Inventor score
Top patents by PatentIndex Score
35 records- 0199US7675317B2Integrated circuits with adjustable body bias and power supply circuitryALTERA CORP·Filed 2007·Granted Mar 9, 2010·128 cites·18 claims
- 0297US7639067B1Integrated circuit voltage regulatorALTERA CORP·Filed 2006·Granted Dec 29, 2009·45 cites·20 claims
- 0395US7355437B2Latch-up prevention circuitry for integrated circuits with transistor body biasingALTERA CORP·Filed 2006·Granted Apr 8, 2008·29 cites·24 claims
- 0494US7920410B1Memory elements with increased write margin and soft error upset immunityALTERA CORP·Filed 2009·Granted Apr 5, 2011·43 cites·11 claims
- 0593US7330049B2Adjustable transistor body bias generation circuitry with latch-up preventionALTERA CORP·Filed 2006·Granted Feb 12, 2008·24 cites·30 claims
- 0692US7639041B1Hotsocket-compatible body bias circuitry with power-up current reduction capabilitiesALTERA CORP·Filed 2008·Granted Dec 29, 2009·21 cites·23 claims
- 0790US7571413B1Testing circuitry for programmable logic devices with selectable power supply voltagesALTERA CORP·Filed 2006·Granted Aug 4, 2009·21 cites·17 claims
- 0889US7592832B2Adjustable transistor body bias circuitryALTERA CORP·Filed 2008·Granted Sep 22, 2009·14 cites·21 claims
- 0989US7514953B2Adjustable transistor body bias generation circuitry with latch-up preventionALTERA CORP·Filed 2007·Granted Apr 7, 2009·14 cites·20 claims
- 1089US7501849B2Latch-up prevention circuitry for integrated circuits with transistor body biasingALTERA CORP·Filed 2008·Granted Mar 10, 2009·15 cites·20 claims
- 1188US7405589B2Apparatus and methods for power management in integrated circuitsALTERA CORP·Filed 2005·Granted Jul 29, 2008·13 cites·23 claims
- 1287US7495471B2Adjustable transistor body bias circuitryALTERA CORP·Filed 2006·Granted Feb 24, 2009·13 cites·26 claims
- 1383US8482963B1Integrated circuits with asymmetric and stacked transistorsLIU JUN·Filed 2009·Granted Jul 9, 2013·11 cites·20 claims
- 1481US9496268B2Integrated circuits with asymmetric and stacked transistorsALTERA CORP·Filed 2014·Granted Nov 15, 2016·4 cites·9 claims
- 1580US8369175B1Memory elements with voltage overstress protectionALTERA CORP·Filed 2010·Granted Feb 5, 2013·7 cites·24 claims
- 1680US7978450B1Electrostatic discharge protection circuitryALTERA CORP·Filed 2008·Granted Jul 12, 2011·10 cites·18 claims
- 1778US7990664B1Electrostatic discharge protection in a field programmable gate arrayALTERA CORP·Filed 2006·Granted Aug 2, 2011·7 cites·21 claims
- 1878US7863968B1Variable-output current-load-independent negative-voltage regulatorALTERA CORP·Filed 2008·Granted Jan 4, 2011·10 cites·17 claims
- 1978US7511932B1ESD protection structureALTERA CORP·Filed 2007·Granted Mar 31, 2009·7 cites·20 claims
- 2076US8279660B2Static random-access memory with boosted voltagesPERISETTY SRINIVAS·Filed 2011·Granted Oct 2, 2012·5 cites·10 claims
- 2175US9735779B1Apparatus and methods for on-die temperature sensing to improve FPGA performancePERISETTY SRINIVAS·Filed 2009·Granted Aug 15, 2017·5 cites·20 claims
- 2271US8618786B1Self-biased voltage regulation circuitry for memoryPERISETTY SRINIVAS·Filed 2009·Granted Dec 31, 2013·8 cites·16 claims
- 2371US6879535B1Approach for zero dummy byte flash memory read operationATMEL CORP·Filed 2004·Granted Apr 12, 2005·18 cites·15 claims
- 2469US11665031B1Tuning analog front end response for jitter tolerance marginsSYNOPSYS INC·Filed 2021·Granted May 30, 2023·1 cites·20 claims
- 2568US8732635B2Apparatus and methods for power management in integrated circuitsLEWIS DAVID·Filed 2008·Granted May 20, 2014·2 cites·20 claims
- 2665US8099704B1Performance improvements in an integrated circuit by selectively applying forward bias voltagesPERISETTY SRINIVAS·Filed 2008·Granted Jan 17, 2012·3 cites·20 claims
- 2765US7629831B1Booster circuit with capacitor protection circuitryALTERA CORP·Filed 2006·Granted Dec 8, 2009·9 cites·15 claims
- 2863US7782581B1Method and apparatus for providing electrostatic discharge protection for a polysilicon fuseALTERA CORP·Filed 2007·Granted Aug 24, 2010·2 cites·26 claims
- 2959US7957177B2Static random-access memory with boosted voltagesALTERA CORP·Filed 2008·Granted Jun 7, 2011·3 cites·13 claims
- 3057US8750026B1Integrated circuits with asymmetric and stacked transistorsALTERA CORP·Filed 2013·Granted Jun 10, 2014·1 cites·20 claims
- 3153US10200037B2Apparatus and methods for on-die temperature sensing to improve FPGA performanceALTERA CORP·Filed 2017·Granted Feb 5, 2019·0 cites·19 claims
- 3253US8711614B1Memory elements with increased write margin and soft error upset immunityLEE ANDY L·Filed 2011·Granted Apr 29, 2014·1 cites·19 claims
- 3351US2014258956A1Apparatus and methods for power management in integrated circuitsALTERA CORP·Filed 2014·Application pending·0 cites
- 3437US2009072891A1Varactor-based charge pumpPERISETTY SRINIVAS·Filed 2007·Application pending·0 cites
- 3535US7296196B2Redundant column read in a memory arrayATMEL CORP·Filed 2005·Granted Nov 13, 2007·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →