Inventor · disambiguated record
Srinath Sridharan
Also filed as: SRIDHARAN SRINATH
23 granted patents·4 pending applications·226 citations·filing 2004–2024
94Inventor score
Files withSHAOXING YUANFANG SEMICONDUCTOR CO LTD5AURA SEMICONDUCTOR PVT LTD4FUSION IO INC2GANTI RAMKISHORE2GUPTA GAGAN2
Top patents by PatentIndex Score
27 records- 0198US9047178B2Auto-commit memory synchronizationFUSION IO INC·Filed 2012·Granted Jun 2, 2015·113 cites·23 claims
- 0297US9218278B2Auto-commit memoryFUSION IO INC·Filed 2013·Granted Dec 22, 2015·64 cites·22 claims
- 0390US11588489B1Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lockSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Feb 21, 2023·5 cites·20 claims
- 0483US10514720B1Hitless switching when generating an output clock derived from multiple redundant input clocksAURA SEMICONDUCTOR PVT LTD·Filed 2019·Granted Dec 24, 2019·5 cites·20 claims
- 0578US9124354B2Isolation and protection circuit for a receiver in a wireless communication deviceGANTI RAMKISHORE·Filed 2012·Granted Sep 1, 2015·6 cites·25 claims
- 0677US12261609B1Inter-PLL communication in a multi-PLL environmentSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2023·Granted Mar 25, 2025·1 cites·20 claims
- 0777US7609781B2Wireless communication device with self calibration feature for controlling power outputST ERICSSON SA·Filed 2006·Granted Oct 27, 2009·6 cites·29 claims
- 0874US7697901B2Digital variable gain mixerST ERICSSON SA·Filed 2006·Granted Apr 13, 2010·5 cites·24 claims
- 0969US10892765B1Relocking a phase locked loop upon cycle slips between input and feedback clocksAURA SEMICONDUCTOR PVT LTD·Filed 2020·Granted Jan 12, 2021·1 cites·20 claims
- 1068US8892159B2Multi-standard transceiver architecture with common balun and mixerGANTI RAMKISHORE·Filed 2012·Granted Nov 18, 2014·3 cites·11 claims
- 1167US9223674B2Computer system and method for runtime control of parallelism in program executionWISCONSIN ALUMNI RES FOUND·Filed 2013·Granted Dec 29, 2015·2 cites·22 claims
- 1267US8787597B2Pop-up noise suppression in audioRANGANATHAN SANJEEV·Filed 2010·Granted Jul 22, 2014·3 cites·7 claims
- 1366US12149255B2Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailableSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2024·Granted Nov 19, 2024·0 cites·6 claims
- 1466US9830157B2System and method for selectively delaying execution of an operation based on a search for uncompleted predicate operations in processor-associated queuesGUPTA GAGAN·Filed 2010·Granted Nov 28, 2017·3 cites·16 claims
- 1564US8843932B2System and method for controlling excessive parallelism in multiprocessor systemsSOHI GURINDAR S·Filed 2011·Granted Sep 23, 2014·3 cites·15 claims
- 1658US11967965B2Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailableSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Apr 23, 2024·0 cites·13 claims
- 1748US7205828B2Voltage regulator having a compensated load conductanceSILICON LAB INC·Filed 2004·Granted Apr 17, 2007·6 cites·20 claims
- 1848US2025259006A1Generating communication summaries using artificial intelligence models, summary templates, and enriched transcriptsQUALTRICS LLC·Filed 2024·Application pending·0 cites
- 1947US9277315B2Pop-up noise suppression in audioST ERICSSON INDIA PVT LTD·Filed 2014·Granted Mar 1, 2016·0 cites·12 claims
- 2047US2025259625A1Generating and providing communication-related recommendations during communications for real-time agent assistanceQUALTRICS LLC·Filed 2024·Application pending·0 cites
- 2140US9742414B2Reducing errors due to non-linearities caused by a phase frequency detector of a phase locked loopAURA SEMICONDUCTOR PVT LTD·Filed 2015·Granted Aug 22, 2017·0 cites·20 claims
- 2240US2007072652A1Controlling power output of a transceiverSHAN SHENG-MING·Filed 2006·Application pending·0 cites
- 2337US8787588B2Coupling of speakers with integrated circuitRANGANATHAN SANJEEV·Filed 2010·Granted Jul 22, 2014·0 cites·8 claims
- 2436US11923864B2Fast switching of output frequency of a phase locked loop (PLL)SHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Mar 5, 2024·0 cites·14 claims
- 2535US9652301B2System and method providing run-time parallelization of computer software using data associated tokensGUPTA GAGAN·Filed 2010·Granted May 16, 2017·0 cites·10 claims
- 2630US2016336923A1Phase locked loop with low phase-noiseAURA SEMICONDUCTOR PVT LTD·Filed 2016·Application pending·0 cites
- 2728US8085080B2Generation of a low jitter clock signalSRIDHARAN SRINATH·Filed 2010·Granted Dec 27, 2011·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →