Inventor · disambiguated record
Stanton Petree Ashburn
Also filed as: ASHBURN STANTON · ASHBURN STANTON P · ASHBURN STANTON PETREE
12 granted patents·6 pending applications·415 citations·filing 1992–2016
92Inventor score
Files withTEXAS INSTRUMENTS INC9UNIV NORTH CAROLINA STATE2ASHBURN STANTON PETREE1PIOUS BEENA1RAVAL JAYESH C1
Top patents by PatentIndex Score
18 records- 0193US5242847ASelective deposition of doped silion-germanium alloy on semiconductor substrateUNIV NORTH CAROLINA STATE·Filed 1992·Granted Sep 7, 1993·159 cites·20 claims
- 0286US6030874ADoped polysilicon to retard boron diffusion into and through thin gate dielectricsTEXAS INSTRUMENTS INC·Filed 1998·Granted Feb 29, 2000·70 cites·5 claims
- 0378US5336903ASelective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structuresUNIV NORTH CAROLINA STATE·Filed 1993·Granted Aug 9, 1994·55 cites·12 claims
- 0477US6054343ANitride trench fill process for increasing shallow trench isolation (STI) robustnessTEXAS INSTRUMENTS INC·Filed 1999·Granted Apr 25, 2000·53 cites·10 claims
- 0575US8693271B2Method of stressing static random access memories for pass transistor defectsRAVAL JAYESH C·Filed 2012·Granted Apr 8, 2014·11 cites·19 claims
- 0670US6326281B1Integrated circuit isolationTEXAS INSTRUMENTS INC·Filed 1999·Granted Dec 4, 2001·37 cites·3 claims
- 0763US9305664B2Memory repair categorization trackingTEXAS INSTRUMENTS INC·Filed 2014·Granted Apr 5, 2016·3 cites·10 claims
- 0854US8526253B2Method of screening static random access memories for pass transistor defectsPIOUS BEENA·Filed 2011·Granted Sep 3, 2013·2 cites·20 claims
- 0953US6433392B1Electrostatic discharge device and methodTEXAS INSTRUMENTS INC·Filed 1999·Granted Aug 13, 2002·12 cites·2 claims
- 1053US6306690B1Process flow to integrate high and low voltage peripheral transistors with a floating gate arrayTEXAS INSTRUMENTS INC·Filed 1999·Granted Oct 23, 2001·12 cites·10 claims
- 1143US7456477B2Electrostatic discharge device and methodTEXAS INSTRUMENTS INC·Filed 2002·Granted Nov 25, 2008·1 cites·2 claims
- 1240US9378848B2Methods and devices for determining logical to physical mapping on an integrated circuitASHBURN STANTON PETREE·Filed 2012·Granted Jun 28, 2016·0 cites·13 claims
- 1340US2004169236A1Process to improve Nwell-Nwell isolation with a blanket low dose high energy implantTEXAS INSTRUMENTS INC·Filed 2004·Application pending·0 cites
- 1438US2002086499A1Process to improve Nwell-Nwell isolation with a blanket low dose high energy implantFiled 2001·Application pending·0 cites
- 1536US2002070421A1Embedded gettering layer in shallow trench isolation structureFiled 2002·Application pending·0 cites
- 1634US2016245861A1Methods and devices for determining logical to physical mapping on an integrated circuitTEXAS INSTRUMENTS INC·Filed 2016·Application pending·0 cites
- 1733US2002072237A1Method for unpatterned resist etch back of shallow trench isolation refill insulatorFiled 2000·Application pending·0 cites
- 1824US2001053583A1Shallow trench isolation formation process using a sacrificial layerFiled 2000·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →