Inventor · disambiguated record
Stephen D. Brown
Also filed as: BROWN STEPHEN · BROWN STEPHEN D · BROWN STEPHEN DOUGLAS
42 granted patents·3 pending applications·736 citations·filing 1977–2017
98Inventor score
Top patents by PatentIndex Score
45 records- 0197US6323680B1Programmable logic device configured to accommodate multiplicationALTERA CORP·Filed 2000·Granted Nov 27, 2001·113 cites·33 claims
- 0295US7669157B1Method and apparatus for performing incremental compilation using top-down and bottom-up design approachesALTERA CORP·Filed 2006·Granted Feb 23, 2010·28 cites·21 claims
- 0394US7500216B1Method and apparatus for performing physical synthesis hill-climbing on multi-processor machinesALTERA CORP·Filed 2007·Granted Mar 3, 2009·42 cites·27 claims
- 0494US4203600ATarget with removable score sheetBROWN STEPHEN D·Filed 1977·Granted May 20, 1980·87 cites·4 claims
- 0590US8296696B1Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesisCHIU GORDON RAYMOND·Filed 2008·Granted Oct 23, 2012·24 cites·21 claims
- 0688US7594208B1Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usageALTERA CORP·Filed 2006·Granted Sep 22, 2009·18 cites·31 claims
- 0787US4876506AApparatus and method for inspecting the profile of the inner wall of a tube employing a wall follower and an eddy current probeWESTINGHOUSE ELECTRIC CORP·Filed 1988·Granted Oct 24, 1989·50 cites·24 claims
- 0886US8985027B2Zip line apparatusBROWN STEPHEN DOUGLAS·Filed 2010·Granted Mar 24, 2015·12 cites·15 claims
- 0985US10023207B2Zip line apparatusNORTH STAY LLC·Filed 2014·Granted Jul 17, 2018·9 cites·21 claims
- 1085US7996797B1Method and apparatus for performing multiple stage physical synthesisALTERA CORP·Filed 2007·Granted Aug 9, 2011·10 cites·32 claims
- 1185US7254801B1Synthesis aware placement: a novel approach that combines knowledge of possible resynthesisALTERA CORP·Filed 2005·Granted Aug 7, 2007·15 cites·40 claims
- 1284US8856702B1Method and apparatus for performing multiple stage physical synthesisALTERA CORP·Filed 2013·Granted Oct 7, 2014·5 cites·21 claims
- 1384US8510688B1Method and apparatus for performing multiple stage physical synthesisSINGH DESHANAND·Filed 2011·Granted Aug 13, 2013·6 cites·19 claims
- 1484US8095914B1Methods for instruction trace decompositionSINGH DESHANAND·Filed 2007·Granted Jan 10, 2012·15 cites·16 claims
- 1583US8589849B1Method and apparatus for implementing soft constraints in tools used for designing programmable logic devicesBORER TERRY·Filed 2007·Granted Nov 19, 2013·10 cites·30 claims
- 1683US6779169B1Method and apparatus for placement of components onto programmable logic devicesALTERA CORP·Filed 2002·Granted Aug 17, 2004·32 cites·24 claims
- 1782US7464362B1Method and apparatus for performing incremental compilationALTERA CORP·Filed 2006·Granted Dec 9, 2008·12 cites·17 claims
- 1880US7318210B1Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arraysALTERA CORP·Filed 2006·Granted Jan 8, 2008·8 cites·26 claims
- 1979US7360190B1Method and apparatus for performing retiming on field programmable gate arraysALTERA CORP·Filed 2004·Granted Apr 15, 2008·25 cites·31 claims
- 2079US7191426B1Method and apparatus for performing incremental compilation on field programmable gate arraysALTERA CORP·Filed 2004·Granted Mar 13, 2007·27 cites·32 claims
- 2177US7181703B1Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usageALTERA CORP·Filed 2003·Granted Feb 20, 2007·22 cites·21 claims
- 2276US7620925B1Method and apparatus for performing post-placement routability optimizationALTERA CORP·Filed 2006·Granted Nov 17, 2009·7 cites·16 claims
- 2375US8250505B1Method and apparatus for performing incremental compilation using top-down and bottom-up design approachesBORER TERRY·Filed 2009·Granted Aug 21, 2012·5 cites·17 claims
- 2474US7194720B1Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devicesALTERA CORP·Filed 2003·Granted Mar 20, 2007·19 cites·26 claims
- 2571US7509597B1Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagramsALTERA CORP·Filed 2005·Granted Mar 24, 2009·5 cites·19 claims
- 2671US7444613B1Systems and methods for mapping arbitrary logic functions into synchronous embedded memoriesALTERA CORP·Filed 2006·Granted Oct 28, 2008·4 cites·38 claims
- 2771US7412677B1Detecting reducible registersALTERA CORP·Filed 2006·Granted Aug 12, 2008·5 cites·30 claims
- 2869US6173551B1Ink jet coder system and methodPHILIP MORRIS INC·Filed 1998·Granted Jan 16, 2001·36 cites·5 claims
- 2967US9754065B2Method and apparatus for implementing soft constraints in tools used for designing programmable logic devicesALTERA CORP·Filed 2013·Granted Sep 5, 2017·1 cites·20 claims
- 3067US7181717B1Method and apparatus for placement of components onto programmable logic devicesALTERA CORP·Filed 2004·Granted Feb 20, 2007·10 cites·16 claims
- 3166US8589838B1M/A for performing incremental compilation using top-down and bottom-up design approachesBORER TERRY·Filed 2012·Granted Nov 19, 2013·1 cites·24 claims
- 3264US7797666B1Systems and methods for mapping arbitrary logic functions into synchronous embedded memoriesALTERA CORP·Filed 2008·Granted Sep 14, 2010·2 cites·20 claims
- 3363US7594204B1Method and apparatus for performing layout-driven optimizations on field programmable gate arraysALTERA CORP·Filed 2003·Granted Sep 22, 2009·8 cites·17 claims
- 3463US6371824B1Yo-yo and method for using a yo-yoFLAMBEAU PRODUCTS CORP·Filed 2000·Granted Apr 16, 2002·9 cites·9 claims
- 3562US7197734B1Method and apparatus for designing systems using logic regionsALTERA CORP·Filed 2002·Granted Mar 27, 2007·12 cites·30 claims
- 3659US9589090B1Method and apparatus for performing multiple stage physical synthesisALTERA CORP·Filed 2014·Granted Mar 7, 2017·0 cites·25 claims
- 3757US9122826B1Method and apparatus for performing compilation using multiple design flowsALTERA CORP·Filed 2013·Granted Sep 1, 2015·0 cites·24 claims
- 3857US7401314B1Method and apparatus for performing compound duplication of components on field programmable gate arraysALTERA CORP·Filed 2005·Granted Jul 15, 2008·1 cites·22 claims
- 3956US2017337318A1Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic DevicesALTERA CORP·Filed 2017·Application pending·0 cites
- 4052US6164040ACartoner with ink jet coderPHILIP MORRIS INC·Filed 1998·Granted Dec 26, 2000·15 cites·9 claims
- 4151US7389489B1Techniques for editing circuit design files to be compatible with a new programmable ICALTERA CORP·Filed 2004·Granted Jun 17, 2008·6 cites·18 claims
- 4249US2012054165A1Electronic Medical Record Mobile Access PackageBROWN STEPHEN D·Filed 2011·Application pending·0 cites
- 4346US5792014AVolleyball training apparatus and methodFiled 1997·Granted Aug 11, 1998·19 cites·12 claims
- 4443US2015189429A1Method and apparatus for the production of sound using a slacklineBROWN STEPHEN DOUGLAS·Filed 2014·Application pending·0 cites
- 4541US6779448B2Method for continuously checking the production of security printing machines, application of said method and device for performing the methodKBA GIORI SA·Filed 2001·Granted Aug 24, 2004·1 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →