Inventor · disambiguated record
Stephen M. Cea
Also filed as: CEA STEPHEN · CEA STEPHEN M
126 granted patents·34 pending applications·1,323 citations·filing 2002–2025
99Inventor score
Top patents by PatentIndex Score
160 records- 0199US7154118B2Bulk non-planar transistor having strained enhanced mobility and methods of fabricationINTEL CORP·Filed 2004·Granted Dec 26, 2006·232 cites·25 claims
- 0298US9583491B2CMOS nanowire structureKIM SEIYON·Filed 2015·Granted Feb 28, 2017·28 cites·15 claims
- 0398US9224810B2CMOS nanowire structureKIM SEIYON·Filed 2011·Granted Dec 29, 2015·44 cites·23 claims
- 0498US9129829B2Silicon and silicon germanium nanowire structuresKUHN KELIN J·Filed 2014·Granted Sep 8, 2015·62 cites·13 claims
- 0598US8847281B2High mobility strained channels for fin-based transistorsCEA STEPHEN M·Filed 2012·Granted Sep 30, 2014·47 cites·22 claims
- 0698US8753942B2Silicon and silicon germanium nanowire structuresKUHN KELIN J·Filed 2010·Granted Jun 17, 2014·144 cites·30 claims
- 0798US7326634B2Bulk non-planar transistor having strained enhanced mobility and methods of fabricationINTEL CORP·Filed 2005·Granted Feb 5, 2008·88 cites·18 claims
- 0897US8211772B2Two-dimensional condensation for uniaxially strained semiconductor finsKAVALIEROS JACK T·Filed 2009·Granted Jul 3, 2012·72 cites·20 claims
- 0996US11824107B2Wrap-around contact structures for semiconductor nanowires and nanoribbonsINTEL CORP·Filed 2022·Granted Nov 21, 2023·2 cites·20 claims
- 1096US10304946B2Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devicesINTEL CORP·Filed 2015·Granted May 28, 2019·11 cites·21 claims
- 1196US9472613B2Conversion of strain-inducing buffer to electrical insulatorINTEL CORP·Filed 2015·Granted Oct 18, 2016·13 cites·20 claims
- 1295US12243875B2Forksheet transistors with dielectric or conductive spineINTEL CORP·Filed 2024·Granted Mar 4, 2025·2 cites·20 claims
- 1395US9224808B2Uniaxially strained nanowire structureCEA STEPHEN M·Filed 2011·Granted Dec 29, 2015·17 cites·43 claims
- 1495US7973389B2Isolated tri-gate transistor fabricated on bulk substrateINTEL CORP·Filed 2009·Granted Jul 5, 2011·23 cites·6 claims
- 1595US7781771B2Bulk non-planar transistor having strained enhanced mobility and methods of fabricationINTEL CORP·Filed 2008·Granted Aug 24, 2010·32 cites·13 claims
- 1694US9608059B2Semiconductor device with isolated body portionCAPPELLANI ANNALISA·Filed 2011·Granted Mar 28, 2017·18 cites·28 claims
- 1794US8120073B2Trigate transistor having extended metal gate electrodeRAKSHIT TITASH·Filed 2008·Granted Feb 21, 2012·35 cites·12 claims
- 1893US10074573B2CMOS nanowire structureINTEL CORP·Filed 2017·Granted Sep 11, 2018·8 cites·18 claims
- 1993US9595581B2Silicon and silicon germanium nanowire structuresINTEL CORP·Filed 2015·Granted Mar 14, 2017·7 cites·19 claims
- 2093US9570614B2Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxationINTEL CORP·Filed 2013·Granted Feb 14, 2017·14 cites·8 claims
- 2193US9564522B2Nanowire structures having non-discrete source and drain regionsCEA STEPHEN M·Filed 2015·Granted Feb 7, 2017·6 cites·9 claims
- 2293US9184294B2High mobility strained channels for fin-based transistorsINTEL CORP·Filed 2014·Granted Nov 10, 2015·11 cites·17 claims
- 2393US9129827B2Conversion of strain-inducing buffer to electrical insulatorCAPPELLANI ANNALISA·Filed 2012·Granted Sep 8, 2015·12 cites·25 claims
- 2493US9087863B2Nanowire structures having non-discrete source and drain regionsCEA STEPHEN M·Filed 2011·Granted Jul 21, 2015·10 cites·17 claims
- 2593US8957476B2Conversion of thin transistor elements from silicon to silicon germaniumGLASS GLENN A·Filed 2012·Granted Feb 17, 2015·16 cites·16 claims
- 2693US8558279B2Non-planar device having uniaxially strained semiconductor body and method of making sameCEA STEPHEN M·Filed 2010·Granted Oct 15, 2013·15 cites·20 claims
- 2792US11527612B2Gate-all-around integrated circuit structures having vertically discrete source or drain structuresINTEL CORP·Filed 2018·Granted Dec 13, 2022·6 cites·13 claims
- 2892US10026829B2Semiconductor device with isolated body portionINTEL CORP·Filed 2017·Granted Jul 17, 2018·8 cites·25 claims
- 2992US8890120B2Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETsKOTLYAR ROZA·Filed 2012·Granted Nov 18, 2014·13 cites·14 claims
- 3092US6982433B2Gate-induced strain for MOS performance improvementINTEL CORP·Filed 2003·Granted Jan 3, 2006·69 cites·25 claims
- 3191US10790281B2Stacked channel structures for MOSFETsINTEL CORP·Filed 2015·Granted Sep 29, 2020·8 cites·25 claims
- 3291US8269283B2Methods and apparatus to reduce layout based strain variations in non-planar transistor structuresCEA STEPHEN M·Filed 2009·Granted Sep 18, 2012·18 cites·8 claims
- 3390US11923370B2Forksheet transistors with dielectric or conductive spineINTEL CORP·Filed 2020·Granted Mar 5, 2024·2 cites·20 claims
- 3490US11404319B2Vertically stacked finFETs and shared gate patterningINTEL CORP·Filed 2017·Granted Aug 2, 2022·5 cites·20 claims
- 3590US11367722B2Stacked nanowire transistor structure with different channel geometries for stressINTEL CORP·Filed 2018·Granted Jun 21, 2022·6 cites·22 claims
- 3689US11581406B2Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layerINTEL CORP·Filed 2021·Granted Feb 14, 2023·1 cites·17 claims
- 3789US10411090B2Hybrid trigate and nanowire CMOS device architectureINTEL CORP·Filed 2015·Granted Sep 10, 2019·6 cites·13 claims
- 3889US10153372B2High mobility strained channels for fin-based NMOS transistorsINTEL CORP·Filed 2014·Granted Dec 11, 2018·5 cites·25 claims
- 3989US2025185316A1Silicon and silicon germanium nanowire structuresSONY GROUP CORP·Filed 2024·Application pending·0 cites
- 4088US8487348B2Methods and apparatus to reduce layout based strain variations in non-planar transistor structuresCEA STEPHEN M·Filed 2012·Granted Jul 16, 2013·8 cites·12 claims
- 4188US6936505B2Method of forming a shallow junctionINTEL CORP·Filed 2003·Granted Aug 30, 2005·43 cites·29 claims
- 4287US11264500B2Device isolationINTEL CORP·Filed 2017·Granted Mar 1, 2022·4 cites·20 claims
- 4387US9935107B2CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the sameINTEL CORP·Filed 2013·Granted Apr 3, 2018·6 cites·20 claims
- 4487US2025324747A1Through gate fin isolationINTEL CORP·Filed 2025·Application pending·0 cites
- 4586US11527640B2Wrap-around contact structures for semiconductor nanowires and nanoribbonsINTEL CORP·Filed 2019·Granted Dec 13, 2022·3 cites·23 claims
- 4686US9905650B2Uniaxially strained nanowire structureINTEL CORP·Filed 2016·Granted Feb 27, 2018·3 cites·20 claims
- 4786US9711598B2Two-dimensional condensation for uniaxially strained semiconductor finsINTEL CORP·Filed 2016·Granted Jul 18, 2017·3 cites·15 claims
- 4886US7019326B2Transistor with strain-inducing structure in channelINTEL CORP·Filed 2003·Granted Mar 28, 2006·35 cites·15 claims
- 4985US10453967B2Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire deviceINTEL CORP·Filed 2015·Granted Oct 22, 2019·3 cites·18 claims
- 5083US12125916B2Nanowire structures having non-discrete source and drain regionsGOOGLE LLC·Filed 2022·Granted Oct 22, 2024·0 cites·7 claims
Showing the top 50 of 160 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →