Inventor · disambiguated record
Stijn Eyerman
Also filed as: EYERMAN STIJN · EYERMAN STIJN ERIK D
11 granted patents·10 pending applications·10 citations·filing 2010–2025
81Inventor score
Top patents by PatentIndex Score
21 records- 0174US10684858B2Indirect memory fetcherINTEL CORP·Filed 2018·Granted Jun 16, 2020·2 cites·20 claims
- 0274US2025321738A1Delayed cache writeback instructions for improved data sharing in manycore processorsINTEL CORP·Filed 2025·Application pending·0 cites
- 0373US10303609B2Independent tuning of multiple hardware prefetchersINTEL CORP·Filed 2017·Granted May 28, 2019·2 cites·17 claims
- 0467US8812808B2Counter architecture for online DVFS profitability estimationEYERMAN STIJN·Filed 2010·Granted Aug 19, 2014·6 cites·13 claims
- 0566US2025355837A1Data access pattern profiler for memory compression scheme selectionINTEL CORP·Filed 2025·Application pending·0 cites
- 0664US2025053454A1Methods and apparatus for a machine learning model decompression acceleratorINTEL CORP·Filed 2024·Application pending·0 cites
- 0764US2025328245A1Variable chunk size memory compressionINTEL CORP·Filed 2025·Application pending·0 cites
- 0861US12333305B2Delayed cache writeback instructions for improved data sharing in manycore processorsINTEL CORP·Filed 2020·Granted Jun 17, 2025·0 cites·14 claims
- 0960US2022229677A1Performance modeling of graph processing computing architecturesINTEL CORP·Filed 2022·Application pending·0 cites
- 1059US11256626B2Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristicsINTEL CORP·Filed 2020·Granted Feb 22, 2022·0 cites·22 claims
- 1159US2025068422A1Method and apparatus for partial virtualization in a processorGALBI DUANE·Filed 2024·Application pending·0 cites
- 1256US12050915B2Instruction and logic for code prefetchingINTEL CORP·Filed 2020·Granted Jul 30, 2024·0 cites·20 claims
- 1355US2025190360A1Os-transparent memory decompression with hardware accelerationINTEL CORP·Filed 2025·Application pending·0 cites
- 1452US10621099B2Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristicsINTEL CORP·Filed 2018·Granted Apr 14, 2020·0 cites·25 claims
- 1547US10942851B2System, apparatus and method for dynamic automatic sub-cacheline granularity memory access controlINTEL CORP·Filed 2018·Granted Mar 9, 2021·0 cites·16 claims
- 1646US2023418612A1Automatic fusion of arithmetic in-flight instructionsINTEL CORP·Filed 2022·Application pending·0 cites
- 1743US10877886B2Storing cache lines in dedicated cache of an idle coreINTEL CORP·Filed 2018·Granted Dec 29, 2020·0 cites·20 claims
- 1841US11526483B2Storage architectures for graph analysis applicationsINTEL CORP·Filed 2018·Granted Dec 13, 2022·0 cites·14 claims
- 1939US11010182B2Instruction window centric processor simulationUNIV GENT·Filed 2013·Granted May 18, 2021·0 cites·11 claims
- 2036US2019004920A1Technologies for processor simulation modeling with machine learningINTEL CORP·Filed 2017·Application pending·0 cites
- 2128US2011295587A1Methods and systems for simulating a processorEECKHOUT LIEVEN·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →