Inventor · disambiguated record
Steven A. Guccione
Also filed as: GUCCIONE STEVEN A · GUCCIONE STEVEN ANTHONY
23 granted patents·2 pending applications·1,635 citations·filing 1997–2016
97Inventor score
Top patents by PatentIndex Score
25 records- 0198US6668237B1Run-time reconfigurable testing of programmable logic devicesXILINX INC·Filed 2002·Granted Dec 23, 2003·161 cites·24 claims
- 0298US6487709B1Run-time routing for programmable logic devicesXILINX INC·Filed 2000·Granted Nov 26, 2002·238 cites·23 claims
- 0395US6836842B1Method of partial reconfiguration of a PLD in which only updated portions of configuration data are selected for reconfiguring the PLDXILINX INC·Filed 2001·Granted Dec 28, 2004·125 cites·16 claims
- 0495US6351143B1Content-addressable memory implemented using programmable logicXILINX INC·Filed 2001·Granted Feb 26, 2002·105 cites·10 claims
- 0595US6078736AMethod of designing FPGAs for dynamically reconfigurable computingXILINX INC·Filed 1997·Granted Jun 20, 2000·230 cites·14 claims
- 0692US6557156B1Method of configuring FPGAS for dynamically reconfigurable computingXILINX INC·Filed 2000·Granted Apr 29, 2003·64 cites·22 claims
- 0790US6922665B1Method and system for device-level simulation of a circuit design for a programmable logic deviceXILINX INC·Filed 2001·Granted Jul 26, 2005·64 cites·20 claims
- 0889US6430736B1Method and apparatus for evolving configuration bitstreamsXILINX INC·Filed 1999·Granted Aug 6, 2002·121 cites·35 claims
- 0987US6212650B1Interactive dubug tool for programmable circuitsXILINX INC·Filed 1997·Granted Apr 3, 2001·133 cites·15 claims
- 1084US6278289B1Content-addressable memory implemented using programmable logicXILINX INC·Filed 2000·Granted Aug 21, 2001·32 cites·11 claims
- 1183US6530071B1Method and apparatus for tolerating defects in a programmable logic device using runtime parameterizable coresXILINX INC·Filed 2000·Granted Mar 4, 2003·37 cites·16 claims
- 1283US6074432AMethod for generating a software class compatible with two or more interpretersXILINX INC·Filed 1998·Granted Jun 13, 2000·103 cites·16 claims
- 1380US5995744ANetwork configuration of programmable circuitsXILINX INC·Filed 1998·Granted Nov 30, 1999·75 cites·26 claims
- 1468US6363519B1Method and apparatus for testing evolvable configuration bitstreamsXILINX INC·Filed 1999·Granted Mar 26, 2002·41 cites·23 claims
- 1567US6216259B1Configuration of programmable logic devices with routing core generatorsXILINX INC·Filed 1998·Granted Apr 10, 2001·39 cites·20 claims
- 1664US6665766B1Adaptable configuration interface for a programmable logic deviceXILINX INC·Filed 2000·Granted Dec 16, 2003·10 cites·12 claims
- 1756US2015187002A1Dual precision compute for monte carlo simulationBANK OF AMERICA·Filed 2014·Application pending·0 cites
- 1850US6539532B1Method and apparatus for relocating elements in an evolvable configuration bitstreamXILINX INC·Filed 1999·Granted Mar 25, 2003·15 cites·12 claims
- 1950US6363517B1Method and apparatus for remotely evolving configuration bitstreamsXILINX INC·Filed 1999·Granted Mar 26, 2002·15 cites·4 claims
- 2050US6144933AMethod and apparatus for remotely probing and stimulating a programmable logic deviceXILINX INC·Filed 1999·Granted Nov 7, 2000·18 cites·37 claims
- 2148US9459832B2Pipelined multiply-scan circuitBANK OF AMERICA·Filed 2014·Granted Oct 4, 2016·0 cites·20 claims
- 2242US9940166B2Allocating field-programmable gate array (FPGA) resourcesBANK OF AMERICA·Filed 2015·Granted Apr 10, 2018·0 cites·20 claims
- 2341US6378122B1Method and apparatus for evolving a plurality of versions of a configuration bitstream in parallelXILINX INC·Filed 1999·Granted Apr 23, 2002·9 cites·11 claims
- 2440US9600356B2Allocating field-programmable gate array (FPGA) resourcesBANK OF AMERICA·Filed 2015·Granted Mar 21, 2017·0 cites·20 claims
- 2539US2017228274A1System for limiting faults associated with a random sampling simulation method for obtaining numeric valuesBANK OF AMERICA·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →