Inventor · disambiguated record
Steven James Heinrich
Also filed as: HEINRICH STEVEN · HEINRICH STEVEN J · HEINRICH STEVEN JAMES
45 granted patents·3 pending applications·703 citations·filing 1997–2024
98Inventor score
Top patents by PatentIndex Score
48 records- 0199US9262797B2Multi-sample surface processing using one sampleNVIDIA CORP·Filed 2013·Granted Feb 16, 2016·132 cites·16 claims
- 0294US8266383B1Cache miss processing using a defer/replay mechanismMINKIN ALEXANDER L·Filed 2009·Granted Sep 11, 2012·51 cites·20 claims
- 0393US8335892B1Cache arbitration between multiple clientsMINKIN ALEXANDER L·Filed 2009·Granted Dec 18, 2012·47 cites·20 claims
- 0492US11080051B2Techniques for efficiently transferring data to a processorNVIDIA CORP·Filed 2019·Granted Aug 3, 2021·9 cites·26 claims
- 0592US10699427B2Method and apparatus for obtaining sampled positions of texturing operationsNVIDIA CORP·Filed 2019·Granted Jun 30, 2020·9 cites·20 claims
- 0692US6278645B1High speed video frame buffer3DLABS INC LTD·Filed 1998·Granted Aug 21, 2001·96 cites·18 claims
- 0791US10424074B1Method and apparatus for obtaining sampled positions of texturing operationsNVIDIA CORP·Filed 2018·Granted Sep 24, 2019·7 cites·20 claims
- 0889US9952977B2Cache operations and policies for a multi-threaded clientHEINRICH STEVEN JAMES·Filed 2010·Granted Apr 24, 2018·21 cites·25 claims
- 0989US6667744B2High speed video frame buffer3DLABS INC LTD·Filed 2001·Granted Dec 23, 2003·36 cites·8 claims
- 1089US6476816B1Multi-processor graphics accelerator3DLABS INC LTD·Filed 1999·Granted Nov 5, 2002·80 cites·32 claims
- 1188US6535216B1Multi-processor graphics accelerator3DLABS INC LTD·Filed 2002·Granted Mar 18, 2003·32 cites·10 claims
- 1285US6642928B1Multi-processor graphics accelerator3DLABS INC LTD·Filed 2002·Granted Nov 4, 2003·32 cites·21 claims
- 1384US9633458B2Method and system for reducing a polygon bounding boxSTEINER WALTER R·Filed 2012·Granted Apr 25, 2017·10 cites·20 claims
- 1484US9223578B2Coalescing memory barrier operations across multiple parallel threadsNICKOLLS JOHN R·Filed 2010·Granted Dec 29, 2015·8 cites·21 claims
- 1583US9262174B2Dynamic bank mode addressing for memory accessFETTERMAN MICHAEL·Filed 2012·Granted Feb 16, 2016·8 cites·24 claims
- 1683US8997103B2N-way memory barrier operation coalescingGADRE SHIRISH·Filed 2012·Granted Mar 31, 2015·9 cites·18 claims
- 1782US8266382B1Cache interface protocol including arbitration and hintsMINKIN ALEXANDER L·Filed 2009·Granted Sep 11, 2012·12 cites·20 claims
- 1880US10459861B2Unified cache for diverse memory trafficNVIDIA CORP·Filed 2017·Granted Oct 29, 2019·2 cites·21 claims
- 1979US8522000B2Trap handler architecture for a parallel processing unitSHEBANOW MICHAEL C·Filed 2009·Granted Aug 27, 2013·11 cites·20 claims
- 2078US10095548B2Mechanism for waking common resource requests within a resource management subsystemFETTERMAN MICHAEL·Filed 2012·Granted Oct 9, 2018·5 cites·21 claims
- 2177US11720440B2Error containment for enabling local checkpoint and recoveryNVIDIA CORP·Filed 2021·Granted Aug 8, 2023·1 cites·19 claims
- 2277US2024378792A1Transcoding compressed texture sets to textures with a hardware-supported compression formatNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2377US2024378759A1Decompression of compressed texture setsNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2476US11379944B2Techniques for performing accelerated point sampling in a texture processing pipelineNVIDIA CORP·Filed 2020·Granted Jul 5, 2022·1 cites·20 claims
- 2576US9946666B2Coalescing texture access and load/store operationsNVIDIA CORP·Filed 2013·Granted Apr 17, 2018·4 cites·17 claims
- 2674US11768686B2Out of order memory request tracking structure and techniqueNVIDIA CORP·Filed 2020·Granted Sep 26, 2023·1 cites·36 claims
- 2774US5864512AHigh-speed video frame buffer using single port memory chipsINTERGRAPH CORP·Filed 1997·Granted Jan 26, 1999·44 cites·25 claims
- 2873US9595075B2Load/store operations in texture hardwareNVIDIA CORP·Filed 2013·Granted Mar 14, 2017·3 cites·20 claims
- 2969US11604649B2Techniques for efficiently transferring data to a processorNVIDIA CORP·Filed 2021·Granted Mar 14, 2023·0 cites·11 claims
- 3068US9286659B2Multi-sample surface processing using sample subsetsNVIDIA CORP·Filed 2013·Granted Mar 15, 2016·2 cites·20 claims
- 3166US11347668B2Unified cache for diverse memory trafficNVIDIA CORP·Filed 2020·Granted May 31, 2022·0 cites·20 claims
- 3263US11907717B2Techniques for efficiently transferring data to a processorNVIDIA CORP·Filed 2023·Granted Feb 20, 2024·0 cites·21 claims
- 3363US11823318B2Techniques for interleaving texturesNVIDIA CORP·Filed 2021·Granted Nov 21, 2023·0 cites·17 claims
- 3462US8595425B2Configurable cache for multiple clientsMINKIN ALEXANDER L·Filed 2009·Granted Nov 26, 2013·2 cites·20 claims
- 3561US10007527B2Uniform load processing for parallel thread sub-setsFETTERMAN MICHAEL·Filed 2012·Granted Jun 26, 2018·1 cites·20 claims
- 3661US9755994B2Mechanism for tracking age of common resource requests within a resource management subsystemFETTERMAN MICHAEL·Filed 2012·Granted Sep 5, 2017·1 cites·22 claims
- 3760US11934311B2Hybrid allocation of data lines in a streaming cache memoryNVIDIA CORP·Filed 2022·Granted Mar 19, 2024·0 cites·21 claims
- 3860US2024257405A1Compression of texture sets using a non-linear function and quantizationNVIDIA CORP·Filed 2024·Application pending·0 cites
- 3959US12314175B2Cache memory with per-sector cache residency controlsNVIDIA CORP·Filed 2022·Granted May 27, 2025·0 cites·20 claims
- 4059US6700576B1Variable stride circle rendering apparatus and method3DLABS INC LTD·Filed 2000·Granted Mar 2, 2004·8 cites·33 claims
- 4157US10705994B2Unified cache for diverse memory trafficNVIDIA CORP·Filed 2017·Granted Jul 7, 2020·0 cites·20 claims
- 4250US11372548B2Techniques for accessing and utilizing compressed data and its state informationNVIDIA CORP·Filed 2020·Granted Jun 28, 2022·0 cites·26 claims
- 4348US7616200B1System for reducing aliasing on a display device3DLABS INC LTD·Filed 1999·Granted Nov 10, 2009·18 cites·61 claims
- 4446US9448935B2Surface resource view hash for coherent cache operations in texture processing hardwareNVIDIA CORP·Filed 2013·Granted Sep 20, 2016·0 cites·21 claims
- 4544US9817668B2Batched replays of divergent operationsFETTERMAN MICHAEL·Filed 2011·Granted Nov 14, 2017·0 cites·18 claims
- 4643US10152329B2Pre-scheduled replays of divergent operationsFETTERMAN MICHAEL·Filed 2012·Granted Dec 11, 2018·0 cites·21 claims
- 4743US9836325B2Resource management subsystem that maintains fairness and orderFETTERMAN MICHAEL·Filed 2012·Granted Dec 5, 2017·0 cites·21 claims
- 4843US9286256B2Sharing data crossbar for reads and writes in a data cacheMINKIN ALEXANDER L·Filed 2010·Granted Mar 15, 2016·0 cites·28 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →