Inventor · disambiguated record
Steven J. Hnatko
Also filed as: HNATKO STEVEN J
13 granted patents·2 pending applications·46 citations·filing 2004–2019
88Inventor score
Top patents by PatentIndex Score
15 records- 0196US9659664B1Dynamically adjusting read voltage in a NAND flash memoryIBM·Filed 2015·Granted May 23, 2017·21 cites·9 claims
- 0288US9691488B1Dynamically adjusting read voltage in a NAND flash memoryIBM·Filed 2016·Granted Jun 27, 2017·7 cites·8 claims
- 0385US8775906B2Efficient storage of meta-bits within a system memoryDODSON JOHN S·Filed 2012·Granted Jul 8, 2014·8 cites·7 claims
- 0473US8635390B2System and method for a hierarchical buffer system for a shared data busHNATKO STEVEN J·Filed 2010·Granted Jan 21, 2014·4 cites·20 claims
- 0568US10223372B2Log synchronization among discrete devices in a computer systemIBM·Filed 2016·Granted Mar 5, 2019·1 cites·18 claims
- 0664US9934865B2Dynamically adjusting read voltage in a NAND flash memoryIBM·Filed 2017·Granted Apr 3, 2018·1 cites·15 claims
- 0757US8874808B2Hierarchical buffer system enabling precise data delivery through an asynchronous boundaryHNATKO STEVEN J·Filed 2012·Granted Oct 28, 2014·2 cites·18 claims
- 0853US10585858B2Log synchronization among discrete devices in a computer systemIBM·Filed 2016·Granted Mar 10, 2020·0 cites·7 claims
- 0952US10990405B2Call/return stack branch target predictor to multiple next sequential instruction addressesIBM·Filed 2019·Granted Apr 27, 2021·0 cites·20 claims
- 1051US11182165B2Skip-over offset branch predictionIBM·Filed 2018·Granted Nov 23, 2021·0 cites·17 claims
- 1151US7290159B2Fixed latency data computation and chip crossing circuits and methods for synchronous input to output protocol translator supporting multiple reference oscillator frequenciesIBM·Filed 2004·Granted Oct 30, 2007·2 cites·20 claims
- 1250US8775904B2Efficient storage of meta-bits within a system memoryDODSON JOHN S·Filed 2011·Granted Jul 8, 2014·0 cites·13 claims
- 1349US9934863B2Dynamically adjusting read voltage in a NAND flash memoryIBM·Filed 2017·Granted Apr 3, 2018·0 cites·14 claims
- 1447US2010005206A1Automatic read data flow control in a cascade interconnect memory systemIBM·Filed 2008·Application pending·0 cites
- 1541US2008307374A1Method, system, and computer program product for mapping a logical design onto an integrated circuit with slack apportionmentIBM·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →