Inventor · disambiguated record
Steven Hsu
Also filed as: HSU STEVEN · HSU STEVEN K
64 granted patents·24 pending applications·716 citations·filing 2001–2025
99Inventor score
Top patents by PatentIndex Score
88 records- 0197US9035686B1Apparatus and method for low power fully-interruptible latches and master-slave flip-flopsINTEL CORP·Filed 2013·Granted May 19, 2015·19 cites·15 claims
- 0296US7838424B2Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etchingTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Nov 23, 2010·84 cites·20 claims
- 0394US9397641B2Apparatus and method for low power fully-interruptible latches and master-slave flip-flopsHSU STEVEN K·Filed 2015·Granted Jul 19, 2016·14 cites·12 claims
- 0493US10473718B2Multibit vectored sequential with scanINTEL CORP·Filed 2017·Granted Nov 12, 2019·4 cites·22 claims
- 0593US9859876B1Shared keeper and footer flip-flopINTEL CORP·Filed 2016·Granted Jan 2, 2018·9 cites·20 claims
- 0693US7332937B2Dynamic logic with adaptive keeperINTEL CORP·Filed 2005·Granted Feb 19, 2008·28 cites·17 claims
- 0792US9960753B2Apparatus and method for low power fully-interruptible latches and master-slave flip-flopsINTEL CORP·Filed 2016·Granted May 1, 2018·7 cites·13 claims
- 0892US7800407B1Multiple voltage mode pre-charging and selective level shiftingINTEL CORP·Filed 2009·Granted Sep 21, 2010·21 cites·20 claims
- 0991US10193536B2Shared keeper and footer flip-flopINTEL CORP·Filed 2018·Granted Jan 29, 2019·6 cites·19 claims
- 1091US9985612B2Time borrowing flip-flop with clock gating scan multiplexerINTEL CORP·Filed 2016·Granted May 29, 2018·4 cites·20 claims
- 1191US9641160B2Common N-well state retention flip-flopINTEL CORP·Filed 2015·Granted May 2, 2017·8 cites·25 claims
- 1289US10177765B2Integrated clock gate circuit with embedded NORINTEL CORP·Filed 2016·Granted Jan 8, 2019·7 cites·14 claims
- 1389US7352209B2Voltage-level converterINTEL CORP·Filed 2006·Granted Apr 1, 2008·15 cites·19 claims
- 1489US7132856B2Hybrid CVSL pass-gate level-converting sequential circuit for multi-Vcc microprocessorsINTEL CORP·Filed 2004·Granted Nov 7, 2006·35 cites·20 claims
- 1589US6628143B2Full-swing source-follower leakage tolerant dynamic logicINTEL CORP·Filed 2001·Granted Sep 30, 2003·36 cites·4 claims
- 1688US10491217B2Low-power clock gate circuitINTEL CORP·Filed 2018·Granted Nov 26, 2019·5 cites·17 claims
- 1788US7855575B1Wide voltage range level shifter with symmetrical switchingINTEL CORP·Filed 2009·Granted Dec 21, 2010·19 cites·20 claims
- 1888US6707708B1Static random access memory with symmetric leakage-compensated bit lineINTEL CORP·Filed 2002·Granted Mar 16, 2004·46 cites·8 claims
- 1988US6563357B1Level converting latchINTEL CORP·Filed 2001·Granted May 13, 2003·35 cites·26 claims
- 2086US6643199B1Memory with reduced sub-threshold leakage current in dynamic bit lines of read portsINTEL CORP·Filed 2002·Granted Nov 4, 2003·39 cites·18 claims
- 2184US6690604B2Register files and caches with digital sub-threshold leakage current calibrationINTEL CORP·Filed 2001·Granted Feb 10, 2004·32 cites·15 claims
- 2283US7606062B2Ultra low voltage and minimum operating voltage tolerant register fileINTEL CORP·Filed 2007·Granted Oct 20, 2009·14 cites·15 claims
- 2381US6844750B2Current mirror based multi-channel leakage current monitor circuit and methodINTEL CORP·Filed 2003·Granted Jan 18, 2005·27 cites·37 claims
- 2481US6762957B2Low clock swing latch for dual-supply voltage designINTEL CORP·Filed 2001·Granted Jul 13, 2004·24 cites·27 claims
- 2579US7002375B2Robust variable keeper strength process-compensated dynamic circuit and methodINTEL CORP·Filed 2003·Granted Feb 21, 2006·22 cites·36 claims
- 2678US7057913B2Low-power search line circuit encoding technique for content addressable memoriesINTEL CORP·Filed 2004·Granted Jun 6, 2006·23 cites·24 claims
- 2777US11398814B2Low-power single-edge triggered flip-flop, and time borrowing internally stitched flip-flopINTEL CORP·Filed 2020·Granted Jul 26, 2022·1 cites·16 claims
- 2874US11442103B2Multibit vectored sequential with scanINTEL CORP·Filed 2021·Granted Sep 13, 2022·0 cites·22 claims
- 2972US6441648B1Double data rate dynamic logicINTEL CORP·Filed 2001·Granted Aug 27, 2002·15 cites·16 claims
- 3070US11757434B2High performance fast Mux-D scan flip-flopINTEL CORP·Filed 2022·Granted Sep 12, 2023·0 cites·17 claims
- 3169US10862462B2Vectored flip-flopINTEL CORP·Filed 2019·Granted Dec 8, 2020·0 cites·20 claims
- 3268US10756736B2Fused voltage level shifting latchINTEL CORP·Filed 2017·Granted Aug 25, 2020·1 cites·19 claims
- 3368US2025377861A1Energy-efficient pre-encoded booth for stationary weights and activationsINTEL CORP·Filed 2025·Application pending·0 cites
- 3467US11054470B1Double edge triggered Mux-D scan flip-flopINTEL CORP·Filed 2019·Granted Jul 6, 2021·0 cites·20 claims
- 3566US9059715B2Voltage level shift with interim-voltage-controlled contention interruptHSU STEVEN K·Filed 2011·Granted Jun 16, 2015·3 cites·17 claims
- 3666US7250783B2Current mirror multi-channel leakage current monitor circuit and methodINTEL CORP·Filed 2004·Granted Jul 31, 2007·12 cites·23 claims
- 3766US6628557B2Leakage-tolerant memory arrangementsINTEL CORP·Filed 2001·Granted Sep 30, 2003·14 cites·17 claims
- 3865US7642129B2Ball-mounting method for coplanarity improvement in large packageTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Jan 5, 2010·3 cites·14 claims
- 3964US2021119616A1Vectored flip-flopINTEL CORP·Filed 2020·Application pending·0 cites
- 4063US6878260B2Process for forming a high-quality interface between a plated and a non-plated areaHTC CORP·Filed 2003·Granted Apr 12, 2005·3 cites·17 claims
- 4163US6618316B2Pseudo-static single-ended cache cellINTEL CORP·Filed 2001·Granted Sep 9, 2003·12 cites·6 claims
- 4262US7209395B2Low leakage and leakage tolerant stack free multi-ported register fileINTEL CORP·Filed 2004·Granted Apr 24, 2007·11 cites·29 claims
- 4361US10498314B2Vectored flip-flopINTEL CORP·Filed 2016·Granted Dec 3, 2019·0 cites·23 claims
- 4461US6749465B1Card connector with reinforcing structureHTC CORP·Filed 2003·Granted Jun 15, 2004·12 cites·20 claims
- 4561US6693461B2Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipationINTEL CORP·Filed 2001·Granted Feb 17, 2004·9 cites·21 claims
- 4661US2024337692A1Configurable Storage Circuits And MethodsINTEL CORP·Filed 2024·Application pending·0 cites
- 4760US11009549B2Multibit vectored sequential with scanINTEL CORP·Filed 2019·Granted May 18, 2021·0 cites·24 claims
- 4859US11296681B2High performance fast Mux-D scan flip-flopINTEL CORP·Filed 2019·Granted Apr 5, 2022·0 cites·20 claims
- 4959US2025309871A1High-performance pulsed latch and clock generation for pulsed latch architecturesINTEL CORP·Filed 2024·Application pending·0 cites
- 5057US6404234B1Variable virtual ground domino logic with leakage controlINTEL CORP·Filed 2001·Granted Jun 11, 2002·7 cites·22 claims
Showing the top 50 of 88 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →