Inventor · disambiguated record
Stefan Macheiner
Also filed as: MACHEINER STEFAN
14 granted patents·3 pending applications·28 citations·filing 2010–2024
87Inventor score
Top patents by PatentIndex Score
17 records- 0184US8704269B2Die packageMACHEINER STEFAN·Filed 2010·Granted Apr 22, 2014·9 cites·21 claims
- 0283US9087829B2Semiconductor arrangementMACHEINER STEFAN·Filed 2011·Granted Jul 21, 2015·8 cites·16 claims
- 0380US11469161B2Lead frame-based semiconductor packageINFINEON TECHNOLOGIES AG·Filed 2020·Granted Oct 11, 2022·1 cites·23 claims
- 0478US11101201B2Semiconductor package having leads with a negative standoffINFINEON TECHNOLOGIES AG·Filed 2019·Granted Aug 24, 2021·2 cites·16 claims
- 0576US11133281B2Chip to chip interconnect in encapsulant of molded semiconductor packageINFINEON TECHNOLOGIES AG·Filed 2019·Granted Sep 28, 2021·2 cites·10 claims
- 0675US10147703B2Semiconductor package for multiphase circuitry deviceINFINEON TECHNOLOGIES AG·Filed 2017·Granted Dec 4, 2018·3 cites·23 claims
- 0775US9385059B2Overmolded substrate-chip arrangement with heat sinkINFINEON TECHNOLOGIES AG·Filed 2013·Granted Jul 5, 2016·3 cites·19 claims
- 0867US11862541B2Molded semiconductor package having a negative standoffINFINEON TECHNOLOGIES AG·Filed 2021·Granted Jan 2, 2024·0 cites·17 claims
- 0967US11569196B2Chip to chip interconnect in encapsulant of molded semiconductor packageINFINEON TECHNOLOGIES AG·Filed 2021·Granted Jan 31, 2023·0 cites·12 claims
- 1061US2025105108A1Semiconductor device comprising a semiconductor die sandwiched between two leadframes and a method for fabricating the sameINFINEON TECHNOLOGIES AG·Filed 2024·Application pending·0 cites
- 1160US11342252B2Leadframe leads having fully plated end facesINFINEON TECHNOLOGIES AG·Filed 2020·Granted May 24, 2022·0 cites·18 claims
- 1253US2023095545A1Semiconductor Packages and Methods for Manufacturing ThereofINFINEON TECHNOLOGIES AG·Filed 2022·Application pending·0 cites
- 1347US10796986B2Leadframe leads having fully plated end facesINFINEON TECHNOLOGIES AG·Filed 2016·Granted Oct 6, 2020·0 cites·19 claims
- 1446US11145578B2Semiconductor package with top or bottom side cooling and method for manufacturing the semiconductor packageINFINEON TECHNOLOGIES AG·Filed 2019·Granted Oct 12, 2021·0 cites·20 claims
- 1546US10121753B2Enhanced solder padINFINEON TECHNOLOGIES AG·Filed 2017·Granted Nov 6, 2018·0 cites·20 claims
- 1636US10770399B2Semiconductor package having a filled conductive cavityINFINEON TECHNOLOGIES AG·Filed 2019·Granted Sep 8, 2020·0 cites·17 claims
- 1733US2017213783A1Multi-chip semiconductor power packageINFINEON TECHNOLOGIES AG·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →