Inventor · disambiguated record
Steven J. Pollock
Also filed as: POLLOCK STEVEN · POLLOCK STEVEN J
10 granted patents·2 pending applications·89 citations·filing 2000–2023
88Inventor score
Top patents by PatentIndex Score
12 records- 0191US8489792B2Transaction performance monitoring in a processor bus bridgeBYRNE RICHARD J·Filed 2010·Granted Jul 16, 2013·17 cites·20 claims
- 0290US8352669B2Buffered crossbar switch systemLSI CORP·Filed 2009·Granted Jan 8, 2013·19 cites·13 claims
- 0377US8505013B2Reducing data read latency in a network communications processor architecturePOLLOCK STEVEN·Filed 2010·Granted Aug 6, 2013·8 cites·20 claims
- 0475US9444757B2Dynamic configuration of processing modules in a network communications processor architecturePEKCAN HAKAN I·Filed 2011·Granted Sep 13, 2016·7 cites·14 claims
- 0571US7389368B1Inter-DSP signaling in a multiple DSP environmentAGERE SYSTEMS INC·Filed 2000·Granted Jun 17, 2008·18 cites·29 claims
- 0667US9461930B2Modifying data streams without reordering in a multi-thread, multi-flow network processorINTEL CORP·Filed 2012·Granted Oct 4, 2016·2 cites·20 claims
- 0766US6691190B1Inter-DSP data exchange in a multiple DSP environmentAGERE SYSTEMS INC·Filed 2000·Granted Feb 10, 2004·13 cites·28 claims
- 0860US8949582B2Changing a flow identifier of a packet in a multi-thread, multi-flow network processorLSI CORP·Filed 2012·Granted Feb 3, 2015·1 cites·20 claims
- 0960US7382170B2Programmable delay circuit having reduced insertion delayAGERE SYSTEMS INC·Filed 2006·Granted Jun 3, 2008·4 cites·18 claims
- 1051US2023401109A1Load balancerINTEL CORP·Filed 2023·Application pending·0 cites
- 1141US8677075B2Memory manager for a network communications processor architectureMITAL DEEPAK·Filed 2012·Granted Mar 18, 2014·0 cites·20 claims
- 1237US2015091620A1Reducing current variation when switching clocksLSI CORP·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →