Inventor · disambiguated record
Stephen J. Robinson
Also filed as: ROBINSON STEPHEN · ROBINSON STEPHEN J · ROBINSON STEPHEN JOSEPH
21 granted patents·5 pending applications·44 citations·filing 1974–2024
92Inventor score
Top patents by PatentIndex Score
26 records- 0188US12032485B264-bit virtual addresses having metadata bit(s) and canonicality check that does not fail due to non-canonical values of metadata bit(s)INTEL CORP·Filed 2020·Granted Jul 9, 2024·2 cites·51 claims
- 0284US12443558B2Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data widthINTEL CORP·Filed 2024·Granted Oct 14, 2025·0 cites·21 claims
- 0383US10067762B2Apparatuses, methods, and systems for memory disambiguationINTEL CORP·Filed 2016·Granted Sep 4, 2018·4 cites·24 claims
- 0480US9996487B2Coherent fabric interconnect for use in multiple topologiesINTEL CORP·Filed 2015·Granted Jun 12, 2018·3 cites·26 claims
- 0579US10572260B2Spatial and temporal merging of remote atomic operationsINTEL CORP·Filed 2017·Granted Feb 25, 2020·2 cites·22 claims
- 0679US2025053651A1Microarchitectural mechanisms for the prevention of side-channel attacks using a thread identification (tid) and a privilege level bitINTEL CORP·Filed 2024·Application pending·0 cites
- 0778US9454371B2Micro-architecture for eliminating MOV operationsMADDURI VENKATESWARA·Filed 2012·Granted Sep 27, 2016·7 cites·25 claims
- 0875US12007938B2Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data widthINTEL CORP·Filed 2022·Granted Jun 11, 2024·0 cites·42 claims
- 0972US12130915B2Microarchitectural mechanisms for the prevention of side-channel attacks using a thread identification (TID) and a privilege level bitINTEL CORP·Filed 2022·Granted Oct 29, 2024·0 cites·24 claims
- 1071US11347680B2Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data widthINTEL CORP·Filed 2020·Granted May 31, 2022·0 cites·36 claims
- 1164US11238155B2Microarchitectural mechanisms for the prevention of side-channel attacksINTEL CORP·Filed 2019·Granted Feb 1, 2022·0 cites·24 claims
- 1263US9632907B2Tracking deferred data packets in a debug trace architectureINTEL CORP·Filed 2014·Granted Apr 25, 2017·1 cites·20 claims
- 1360US11500636B2Spatial and temporal merging of remote atomic operationsINTEL CORP·Filed 2020·Granted Nov 15, 2022·0 cites·21 claims
- 1458US10901940B2Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data widthINTEL CORP·Filed 2016·Granted Jan 26, 2021·0 cites·25 claims
- 1558US9785576B2Hardware-assisted virtualization for implementing secure video output pathINTEL CORP·Filed 2014·Granted Oct 10, 2017·1 cites·20 claims
- 1658US9141570B2Enabling virtualization of a processor resourceINTEL CORP·Filed 2014·Granted Sep 22, 2015·0 cites·20 claims
- 1755US9619412B2Enabling virtualization of a processor resourceINTEL CORP·Filed 2015·Granted Apr 11, 2017·0 cites·20 claims
- 1852US9875187B2Interruption of a page miss handlerINTEL CORP·Filed 2014·Granted Jan 23, 2018·0 cites·21 claims
- 1952US2025004768A1Vector packed matrix multiplication and accumulation processors, methods, systems, and instructionsHEINECKE ALEXANDER·Filed 2023·Application pending·0 cites
- 2048US9189360B2Processor that records tracing data in non contiguous system memory slicesSTRONG BEEMAN C·Filed 2013·Granted Nov 17, 2015·0 cites·20 claims
- 2148US3971027ARadio interferometer sector-definitionPHILIPS CORP·Filed 1974·Granted Jul 20, 1976·9 cites·4 claims
- 2243US2022309005A1Memory bandwidth control in a coreINTEL CORP·Filed 2021·Application pending·0 cites
- 2342US2015277949A1Securing shared interconnect for virtual machineLOH THIAM WAH·Filed 2014·Application pending·0 cites
- 2438US5812091ARadio interferometric antenna for angle codingFiled 1997·Granted Sep 22, 1998·15 cites·27 claims
- 2537US2022198023A1Simulation state to detect transient execution attackINTEL CORP·Filed 2020·Application pending·0 cites
- 2634US8533721B2Method and system of scheduling out-of-order operations without the requirement to execute compare, ready and pick logic in a single cycleROBINSON STEPHEN J·Filed 2010·Granted Sep 10, 2013·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →