Inventor · disambiguated record
Stuart Siu
Also filed as: SIU STUART · SIU STUART C
8 granted patents·1 pending application·278 citations·filing 1998–2011
89Inventor score
Files withHEWLETT PACKARD CO2HEWLETT PACKARD DEVELOPMENT CO2STOIBER STEVEN T2ADVANCED RISC MACH LTD1TRANSMETA CORP1
Top patents by PatentIndex Score
9 records- 0193US7330080B1Ring based impedance control of an output driverTRANSMETA CORP·Filed 2004·Granted Feb 12, 2008·50 cites·14 claims
- 0293US6492854B1Power efficient and high performance flip-flopHEWLETT PACKARD CO·Filed 2001·Granted Dec 10, 2002·60 cites·18 claims
- 0387US7889014B1Ring based impedance control of an output driverSTOIBER STEVEN T·Filed 2007·Granted Feb 15, 2011·14 cites·27 claims
- 0486US8624680B2Ring based impedance control of an output driverSTOIBER STEVEN T·Filed 2011·Granted Jan 7, 2014·7 cites·20 claims
- 0582US6918012B2Streamlined cache coherency protocol system and method for a multiple processor single chip deviceHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jul 12, 2005·38 cites·16 claims
- 0679US5881260AMethod and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker within each instructionHEWLETT PACKARD CO·Filed 1998·Granted Mar 9, 1999·96 cites·20 claims
- 0762US6874014B2Chip multiprocessor with multiple operating systemsHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Mar 29, 2005·12 cites·19 claims
- 0848US7830176B2Controlling signal levels on a signal line within an integrated circuitADVANCED RISC MACH LTD·Filed 2006·Granted Nov 9, 2010·1 cites·20 claims
- 0940US2003023794A1Cache coherent split transaction memory bus architecture and protocol for a multi processor chip deviceFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →