Inventor · disambiguated record
Stephen M. Trimberger
Also filed as: TRIMBERGER STEPHEN · TRIMBERGER STEPHEN M
250 granted patents·1 pending application·16,025 citations·filing 1986–2020
99Inventor score
Top patents by PatentIndex Score
251 records- 0199US8536896B1Programmable interconnect element and method of implementing a programmable interconnect elementTRIMBERGER STEPHEN M·Filed 2012·Granted Sep 17, 2013·60 cites·16 claims
- 0299US7328384B1Method and apparatus using device defects as an identifierXILINX INC·Filed 2005·Granted Feb 5, 2008·111 cites·9 claims
- 0399US7212448B1Method and apparatus for multiple context and high reliability operation of programmable logic devicesXILINX INC·Filed 2005·Granted May 1, 2007·224 cites·20 claims
- 0499US6601227B1Method for making large-scale ASIC using pre-engineered long distance routing structureXILINX INC·Filed 2001·Granted Jul 29, 2003·354 cites·24 claims
- 0599US6480954B2Method of time multiplexing a programmable logic deviceXILINX INC·Filed 2001·Granted Nov 12, 2002·318 cites·13 claims
- 0699US6084429APLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arraysXILINX INC·Filed 1998·Granted Jul 4, 2000·360 cites·10 claims
- 0799US5892961AField programmable gate array having programming instructions in the configuration bitstreamXILINX INC·Filed 1997·Granted Apr 6, 1999·295 cites·30 claims
- 0899US5629637AMethod of time multiplexing a programmable logic deviceXILINX INC·Filed 1995·Granted May 13, 1997·295 cites·14 claims
- 0999US5600263AConfiguration modes for a time multiplexed programmable logic deviceXILINX INC·Filed 1995·Granted Feb 4, 1997·285 cites·13 claims
- 1099US5365125ALogic cell for field programmable gate array having optional internal feedback and optional cascadeXILINX INC·Filed 1992·Granted Nov 15, 1994·287 cites·9 claims
- 1198US9225512B1Encryption and decryption using a physically unclonable functionXILINX INC·Filed 2013·Granted Dec 29, 2015·83 cites·15 claims
- 1298US9082514B1Method and apparatus for physically unclonable function burn-inXILINX INC·Filed 2013·Granted Jul 14, 2015·44 cites·20 claims
- 1398US8981810B1Method and apparatus for preventing accelerated aging of a physically unclonable functionXILINX INC·Filed 2013·Granted Mar 17, 2015·44 cites·20 claims
- 1498US8386990B1Unique identifier derived from an intrinsic characteristic of an integrated circuitXILINX INC·Filed 2010·Granted Feb 26, 2013·60 cites·20 claims
- 1598US8176461B1Design-specific performance specification based on a yield for programmable integrated circuitsTRIMBERGER STEPHEN M·Filed 2010·Granted May 8, 2012·111 cites·15 claims
- 1698US7831873B1Method and apparatus for detecting sudden temperature/voltage changes in integrated circuitsXILINX INC·Filed 2007·Granted Nov 9, 2010·130 cites·17 claims
- 1798US7518398B1Integrated circuit with through-die via interface for die stackingXILINX INC·Filed 2007·Granted Apr 14, 2009·62 cites·18 claims
- 1898US7138827B1Programmable logic device with time-multiplexed interconnectXILINX INC·Filed 2004·Granted Nov 21, 2006·174 cites·20 claims
- 1998US6829756B1Programmable logic device with time-multiplexed interconnectXILINX INC·Filed 2002·Granted Dec 7, 2004·198 cites·14 claims
- 2098US6496971B1Supporting multiple FPGA configuration modes using dedicated on-chip processorXILINX INC·Filed 2000·Granted Dec 17, 2002·230 cites·32 claims
- 2198US5978260AMethod of time multiplexing a programmable logic deviceXILINX INC·Filed 1998·Granted Nov 2, 1999·164 cites·56 claims
- 2298US5944813AFPGA input output buffer with registered tristate enableXILINX INC·Filed 1997·Granted Aug 31, 1999·220 cites·6 claims
- 2398US5844422AState saving and restoration in reprogrammable FPGAsXILINX INC·Filed 1996·Granted Dec 1, 1998·226 cites·24 claims
- 2498US5825202AIntegrated circuit with field programmable and application specific logic areasXILINX INC·Filed 1996·Granted Oct 20, 1998·383 cites·20 claims
- 2598US5778439AProgrammable logic device with hierarchical confiquration and state storageXILINX INC·Filed 1995·Granted Jul 7, 1998·226 cites·20 claims
- 2698US5646545ATime multiplexed programmable logic deviceXILINX INC·Filed 1995·Granted Jul 8, 1997·475 cites·65 claims
- 2797US9941880B1Secure voltage regulatorXILINX INC·Filed 2016·Granted Apr 10, 2018·22 cites·19 claims
- 2897US9584329B1Physically unclonable function and helper data indicating unstable bitsXILINX INC·Filed 2014·Granted Feb 28, 2017·66 cites·15 claims
- 2997US8892903B1Detection of power analysis attacksXILINX INC·Filed 2012·Granted Nov 18, 2014·51 cites·20 claims
- 3097US8516339B1Method of and circuit for correcting adjacent bit errors in a memoryLESEA AUSTIN H·Filed 2011·Granted Aug 20, 2013·47 cites·19 claims
- 3197US8427193B1Intellectual property core protection for integrated circuitsTRIMBERGER STEPHEN M·Filed 2010·Granted Apr 23, 2013·25 cites·15 claims
- 3297US7199608B1Programmable logic device and method of configurationXILINX INC·Filed 2005·Granted Apr 3, 2007·49 cites·20 claims
- 3397US6894527B1Evolved circuits for bitstream protectionXILINX INC·Filed 2003·Granted May 17, 2005·152 cites·21 claims
- 3497US6777978B2Structures and methods for selectively applying a well bias to portions of a programmable deviceXILINX INC·Filed 2003·Granted Aug 17, 2004·125 cites·28 claims
- 3597US6621325B2Structures and methods for selectively applying a well bias to portions of a programmable deviceXILINX INC·Filed 2001·Granted Sep 16, 2003·90 cites·21 claims
- 3697US6242947B1PLD having a window pane architecture with segmented interconnect wiring between logic block arraysXILINX INC·Filed 2000·Granted Jun 5, 2001·85 cites·18 claims
- 3797US6094065AIntegrated circuit with field programmable and application specific logic areasXILINX INC·Filed 1998·Granted Jul 25, 2000·183 cites·8 claims
- 3897US5847577ADRAM memory cell for programmable logic devicesXILINX INC·Filed 1996·Granted Dec 8, 1998·157 cites·23 claims
- 3997US5825662AComputer-implemented method of optimizing a time multiplexed programmable logic deviceXILINX INC·Filed 1997·Granted Oct 20, 1998·290 cites·3 claims
- 4097US5815004AMulti-buffered configurable logic block output lines in a field programmable gate arrayXILINX INC·Filed 1995·Granted Sep 29, 1998·192 cites·21 claims
- 4197US5761483AOptimizing and operating a time multiplexed programmable logic deviceXILINX INC·Filed 1995·Granted Jun 2, 1998·339 cites·12 claims
- 4297US5610829AMethod for programming an FPLD using a library-based technology mapping algorithmXILINX INC·Filed 1996·Granted Mar 11, 1997·299 cites·3 claims
- 4397US5583450ASequencer for a time multiplexed programmable logic deviceXILINX INC·Filed 1995·Granted Dec 10, 1996·182 cites·27 claims
- 4497US5521835AMethod for programming an FPLD using a library-based technology mapping algorithmXILINX INC·Filed 1994·Granted May 28, 1996·281 cites·7 claims
- 4597US5426379AField programmable gate array with built-in bitstream data expansionXILINX INC·Filed 1994·Granted Jun 20, 1995·131 cites·25 claims
- 4696US9608827B1Memory cell with de-initialization circuitryXILINX INC·Filed 2016·Granted Mar 28, 2017·20 cites·17 claims
- 4796US8418006B1Protecting a design for an integrated circuit using a unique identifierTRIMBERGER STEPHEN M·Filed 2010·Granted Apr 9, 2013·40 cites·17 claims
- 4896US8098081B1Optimization of interconnection networksTRIMBERGER STEPHEN M·Filed 2010·Granted Jan 17, 2012·18 cites·20 claims
- 4996US7973555B1Configuration interface to stacked FPGAXILINX INC·Filed 2008·Granted Jul 5, 2011·43 cites·11 claims
- 5096US7941673B1Copy protection without non-volatile memoryXILINX INC·Filed 2005·Granted May 10, 2011·39 cites·16 claims
Showing the top 50 of 251 patent records by PatentIndex Score.
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