Inventor · disambiguated record
Steven Tu
Also filed as: TU STEVEN · TU STEVEN J
46 granted patents·13 pending applications·448 citations·filing 1998–2024
98Inventor score
Top patents by PatentIndex Score
59 records- 0191US7406553B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2007·Granted Jul 29, 2008·18 cites·20 claims
- 0291US7055060B2On-die mechanism for high-reliability processorINTEL CORP·Filed 2002·Granted May 30, 2006·85 cites·16 claims
- 0387US8065576B2Test access portMINER DAVID E·Filed 2009·Granted Nov 22, 2011·16 cites·35 claims
- 0486US7404043B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2005·Granted Jul 22, 2008·11 cites·16 claims
- 0584US7957603B2Digital image decoder with integrated concurrent image prescalerINTEL CORP·Filed 2006·Granted Jun 7, 2011·7 cites·15 claims
- 0681US7627797B2Test access portINTEL CORP·Filed 2006·Granted Dec 1, 2009·8 cites·23 claims
- 0780US7944502B2Pipelining techniques for deinterlacing video informationINTEL CORP·Filed 2010·Granted May 17, 2011·5 cites·20 claims
- 0880US7428732B2Method and apparatus for controlling access to shared resources in an environment with multiple logical processorsINTEL CORP·Filed 2001·Granted Sep 23, 2008·36 cites·13 claims
- 0978US7139947B2Test access portINTEL CORP·Filed 2000·Granted Nov 21, 2006·20 cites·27 claims
- 1077US6954886B2Deterministic hardware reset for FRC machineINTEL CORP·Filed 2001·Granted Oct 11, 2005·22 cites·37 claims
- 1175US7428607B2Apparatus and method for arbitrating heterogeneous agents in on-chip bussesMARVELL INT LTD·Filed 2006·Granted Sep 23, 2008·5 cites·16 claims
- 1274US8111932B2Digital image decoder with integrated concurrent image prescalerTU STEVEN J·Filed 2011·Granted Feb 7, 2012·3 cites·20 claims
- 1374US7634603B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2008·Granted Dec 15, 2009·4 cites·17 claims
- 1474US6775748B2Methods and apparatus for transferring cache block ownershipINTEL CORP·Filed 2002·Granted Aug 10, 2004·20 cites·31 claims
- 1573US7464208B2Method and apparatus for shared resource management in a multiprocessing systemINTEL CORP·Filed 2006·Granted Dec 9, 2008·5 cites·18 claims
- 1673US7062613B2Methods and apparatus for cache interventionINTEL CORP·Filed 2005·Granted Jun 13, 2006·5 cites·38 claims
- 1772US7159077B2Direct processor cache access within a system having a coherent multi-processor protocolINTEL CORP·Filed 2004·Granted Jan 2, 2007·16 cites·30 claims
- 1871US7100001B2Methods and apparatus for cache interventionINTEL CORP·Filed 2002·Granted Aug 29, 2006·16 cites·32 claims
- 1971US6684346B2Method and apparatus for machine check abort handling in a multiprocessing systemINTEL CORP·Filed 2000·Granted Jan 27, 2004·14 cites·30 claims
- 2069US2024396711A1Multi-tenancy protection for acceleratorsINTEL CORP·Filed 2024·Application pending·0 cites
- 2168US7194671B2Mechanism handling race conditions in FRC-enabled processorsINTEL CORP·Filed 2001·Granted Mar 20, 2007·14 cites·20 claims
- 2266US7124224B2Method and apparatus for shared resource management in a multiprocessing systemINTEL CORP·Filed 2000·Granted Oct 17, 2006·10 cites·15 claims
- 2366US6983348B2Methods and apparatus for cache interventionINTEL CORP·Filed 2002·Granted Jan 3, 2006·10 cites·24 claims
- 2465US7890790B2Transactional flow management interrupt debug architectureINTEL CORP·Filed 2009·Granted Feb 15, 2011·2 cites·22 claims
- 2564US7620840B2Transactional flow management interrupt debug architectureINTEL CORP·Filed 2006·Granted Nov 17, 2009·2 cites·21 claims
- 2664US7219176B2System and apparatus for early fixed latency subtractive decodingMARVELL INT LTD·Filed 2002·Granted May 15, 2007·6 cites·23 claims
- 2763US7143220B2Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latenciesINTEL CORP·Filed 2004·Granted Nov 28, 2006·6 cites·30 claims
- 2862US6282636B1Decentralized exception processing systemINTEL CORP·Filed 1998·Granted Aug 28, 2001·37 cites·20 claims
- 2961US7290093B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2003·Granted Oct 30, 2007·5 cites·7 claims
- 3060US7216252B1Method and apparatus for machine check abort handling in a multiprocessing systemINTEL CORP·Filed 2003·Granted May 8, 2007·6 cites·30 claims
- 3159US8533401B2Implementing direct access caches in coherent multiprocessorsEDIRISOORIYA SAMANTHA J·Filed 2002·Granted Sep 10, 2013·7 cites·4 claims
- 3259US7464227B2Method and apparatus for supporting opportunistic sharing in coherent multiprocessorsINTEL CORP·Filed 2002·Granted Dec 9, 2008·6 cites·27 claims
- 3356US2022311594A1Multi-tenancy protection for acceleratorsINTEL CORP·Filed 2022·Application pending·0 cites
- 3455US7765349B1Apparatus and method for arbitrating heterogeneous agents in on-chip bussesMARVELL INT LTD·Filed 2008·Granted Jul 27, 2010·0 cites·19 claims
- 3554US7234028B2Power/performance optimized cache using memory write prevention through write snarfingINTEL CORP·Filed 2002·Granted Jun 19, 2007·3 cites·25 claims
- 3653US2024203736A1Reusable templates for semiconductor design and fabricationADVANCED MICRO DEVICES INC·Filed 2022·Application pending·0 cites
- 3752US7640387B2Method and apparatus for implementing heterogeneous interconnectsINTEL CORP·Filed 2008·Granted Dec 29, 2009·0 cites·20 claims
- 3852US7406552B2Systems and methods for early fixed latency subtractive decoding including speculative acknowledgingMARVELL INT LTD·Filed 2007·Granted Jul 29, 2008·0 cites·17 claims
- 3950US7366845B2Pushing of clean data to one or more processors in a system having a coherency protocolINTEL CORP·Filed 2004·Granted Apr 29, 2008·1 cites·38 claims
- 4050US7353317B2Method and apparatus for implementing heterogeneous interconnectsINTEL CORP·Filed 2004·Granted Apr 1, 2008·1 cites·25 claims
- 4149US7952643B2Pipelining techniques for deinterlacing video informationINTEL CORP·Filed 2006·Granted May 31, 2011·0 cites·20 claims
- 4249US7487299B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2005·Granted Feb 3, 2009·0 cites·9 claims
- 4348US7966477B1Power optimized replay of blocked operations in a pipilined architectureMARVELL INT LTD·Filed 2010·Granted Jun 21, 2011·0 cites·14 claims
- 4448US7685379B2Cache memory to support a processor's power mode of operationINTEL CORP·Filed 2005·Granted Mar 23, 2010·0 cites·12 claims
- 4547US7804542B2Spatio-temporal adaptive video de-interlacing for parallel processingINTEL CORP·Filed 2006·Granted Sep 28, 2010·0 cites·21 claims
- 4646US7725683B2Apparatus and method for power optimized replay via selective recirculation of instructionsMARVELL INT LTD·Filed 2003·Granted May 25, 2010·0 cites·18 claims
- 4746US2006112238A1Techniques for pushing data to a processor cacheJAMIL SUJAT·Filed 2004·Application pending·0 cites
- 4845US6412062B1Injection control mechanism for external eventsINTEL CORP·Filed 1999·Granted Jun 25, 2002·16 cites·24 claims
- 4945US2005125582A1Methods and apparatus to dispatch interrupts in multi-processor systemsFiled 2003·Application pending·0 cites
- 5044US8265169B2Video block memory read request translation and taggingTU STEVEN·Filed 2006·Granted Sep 11, 2012·0 cites·12 claims
Showing the top 50 of 59 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →