Inventor · disambiguated record
Steven P. Young
Also filed as: YOUNG STEVEN · YOUNG STEVEN P · YOUNG STEVEN PALMER
215 granted patents·2 pending applications·9,281 citations·filing 1986–2022
99Inventor score
Top patents by PatentIndex Score
217 records- 0199US7965102B1Formation of columnar application specific circuitry using a columnar programmable deviceXILINX INC·Filed 2008·Granted Jun 21, 2011·188 cites·18 claims
- 0299US7499513B1Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuitXILINX INC·Filed 2005·Granted Mar 3, 2009·83 cites·25 claims
- 0399US7193433B1Programmable logic block having lookup table with partial output signal driving carry multiplexerXILINX INC·Filed 2005·Granted Mar 20, 2007·121 cites·16 claims
- 0499US6529040B1FPGA lookup table with speed read decoderXILINX INC·Filed 2000·Granted Mar 4, 2003·241 cites·21 claims
- 0599US6526557B1Architecture and method for partially reconfiguring an FPGAXILINX INC·Filed 2000·Granted Feb 25, 2003·196 cites·25 claims
- 0699US6448808B2Interconnect structure for a programmable logic deviceXILINX INC·Filed 2001·Granted Sep 10, 2002·225 cites·23 claims
- 0799US6362650B1Method and apparatus for incorporating a multiplier into an FPGAXILINX INC·Filed 2000·Granted Mar 26, 2002·210 cites·9 claims
- 0899US5933023AFPGA architecture having RAM blocks with programmable word length and width and dedicated address and data linesXILINX INC·Filed 1996·Granted Aug 3, 1999·262 cites·26 claims
- 0999US5914616AFPGA repeatable interconnect structure with hierarchical interconnect linesXILINX INC·Filed 1997·Granted Jun 22, 1999·495 cites·39 claims
- 1098US9859896B1Distributed multi-die routing in a multi-chip moduleXILINX INC·Filed 2015·Granted Jan 2, 2018·52 cites·20 claims
- 1198US7919845B2Formation of a hybrid integrated circuit deviceXILINX INC·Filed 2007·Granted Apr 5, 2011·188 cites·15 claims
- 1298US7472155B2Programmable logic device with cascading DSP slicesXILINX INC·Filed 2004·Granted Dec 30, 2008·111 cites·44 claims
- 1398US7276934B1Integrated circuit with programmable routing structure including diagonal interconnect linesXILINX INC·Filed 2005·Granted Oct 2, 2007·66 cites·19 claims
- 1498US7218143B1Integrated circuit having fast interconnect paths between memory elements and carry logicXILINX INC·Filed 2005·Granted May 15, 2007·55 cites·20 claims
- 1598US7068072B2Integrated circuit with interface tile for coupling to a stacked-die second integrated circuitXILINX INC·Filed 2003·Granted Jun 27, 2006·312 cites·41 claims
- 1698US6573749B2Method and apparatus for incorporating a multiplier into an FPGAXILINX INC·Filed 2002·Granted Jun 3, 2003·156 cites·19 claims
- 1797US7733123B1Implementing conditional statements in self-timed logic circuitsXILINX INC·Filed 2009·Granted Jun 8, 2010·39 cites·20 claims
- 1897US7218139B1Programmable integrated circuit providing efficient implementations of arithmetic functionsXILINX INC·Filed 2005·Granted May 15, 2007·68 cites·20 claims
- 1997US7202698B1Integrated circuit having a programmable input structure with bounce capabilityXILINX INC·Filed 2005·Granted Apr 10, 2007·47 cites·20 claims
- 2097US6777978B2Structures and methods for selectively applying a well bias to portions of a programmable deviceXILINX INC·Filed 2003·Granted Aug 17, 2004·125 cites·28 claims
- 2197US6621325B2Structures and methods for selectively applying a well bias to portions of a programmable deviceXILINX INC·Filed 2001·Granted Sep 16, 2003·90 cites·21 claims
- 2297US6373779B1Block RAM having multiple configurable write modes for use in a field programmable gate arrayXILINX INC·Filed 2000·Granted Apr 16, 2002·91 cites·27 claims
- 2397US6201406B1FPGA configurable by two types of bitstreamsXILINX INC·Filed 2000·Granted Mar 13, 2001·87 cites·20 claims
- 2497US5963050AConfigurable logic element with fast feedback pathsXILINX INC·Filed 1997·Granted Oct 5, 1999·129 cites·13 claims
- 2596US6768338B1PLD lookup table including transistors of more than one oxide thicknessXILINX INC·Filed 2003·Granted Jul 27, 2004·62 cites·43 claims
- 2696US6759869B1Large crossbar switch implemented in FPGAXILINX INC·Filed 2002·Granted Jul 6, 2004·83 cites·24 claims
- 2796US6154048AStructure and method for loading narrow frames of data from a wide input busXILINX INC·Filed 2000·Granted Nov 28, 2000·73 cites·26 claims
- 2896US5936424AHigh speed bus with tree structure for selecting bus driverXILINX INC·Filed 1997·Granted Aug 10, 1999·128 cites·13 claims
- 2996US5920202AConfigurable logic element with ability to evaluate five and six input functionsXILINX INC·Filed 1997·Granted Jul 6, 1999·121 cites·11 claims
- 3095US7746111B1Gating logic circuits in a self-timed integrated circuitXILINX INC·Filed 2009·Granted Jun 29, 2010·27 cites·20 claims
- 3195US7196543B1Integrated circuit having a programmable input structure with optional fanout capabilityXILINX INC·Filed 2005·Granted Mar 27, 2007·32 cites·20 claims
- 3295US6525565B2Double data rate flip-flopXILINX INC·Filed 2001·Granted Feb 25, 2003·43 cites·11 claims
- 3395US6396303B1Expandable interconnect structure for FPGASXILINX INC·Filed 1999·Granted May 28, 2002·109 cites·17 claims
- 3495US6204689B1Input/output interconnect circuit for FPGAsXILINX INC·Filed 1999·Granted Mar 20, 2001·115 cites·21 claims
- 3594US8058897B1Configuration of a multi-die integrated circuitLU WEIGUANG·Filed 2010·Granted Nov 15, 2011·28 cites·14 claims
- 3694US7605604B1Integrated circuits with novel handshake logicXILINX INC·Filed 2008·Granted Oct 20, 2009·25 cites·20 claims
- 3794US7061271B1Six-input look-up table for use in a field programmable gate arrayXILINX INC·Filed 2004·Granted Jun 13, 2006·58 cites·16 claims
- 3894US7057413B1Large crossbar switch implemented in FPGAXILINX INC·Filed 2004·Granted Jun 6, 2006·65 cites·24 claims
- 3994US6427156B1Configurable logic block with AND gate for efficient multiplication in FPGASXILINX INC·Filed 1997·Granted Jul 30, 2002·106 cites·7 claims
- 4094US6288568B1FPGA architecture with deep look-up table RAMsXILINX INC·Filed 2000·Granted Sep 11, 2001·57 cites·16 claims
- 4194US6255848B1Method and structure for reading, modifying and writing selected configuration memory cells of an FPGAXILINX INC·Filed 1999·Granted Jul 3, 2001·98 cites·15 claims
- 4294US6204690B1FPGA architecture with offset interconnect linesXILINX INC·Filed 2000·Granted Mar 20, 2001·45 cites·11 claims
- 4394US6107826AInterconnect structure for FPGA with configurable delay locked loopXILINX INC·Filed 1998·Granted Aug 22, 2000·94 cites·19 claims
- 4494US5130067AMethod and means for co-sintering ceramic/metal mlc substratesIBM·Filed 1986·Granted Jul 14, 1992·140 cites·21 claims
- 4593US8245102B1Error checking parity and syndrome of a block of data with relocated parity bitsCORY WARREN E·Filed 2008·Granted Aug 14, 2012·23 cites·18 claims
- 4693US7759974B1Pipelined unidirectional programmable interconnect in an integrated circuitXILINX INC·Filed 2008·Granted Jul 20, 2010·24 cites·19 claims
- 4793US7746112B1Output structure with cascaded control signals for logic blocks in integrated circuits, and methods of using the sameXILINX INC·Filed 2009·Granted Jun 29, 2010·23 cites·20 claims
- 4893US7746109B1Circuits for sharing self-timed logicXILINX INC·Filed 2009·Granted Jun 29, 2010·22 cites·20 claims
- 4993US7215138B1Programmable lookup table with dual input and output terminals in shift register modeXILINX INC·Filed 2005·Granted May 8, 2007·25 cites·20 claims
- 5093US6975145B1Glitchless dynamic multiplexer with synchronous and asynchronous controlsXILINX INC·Filed 2003·Granted Dec 13, 2005·69 cites·18 claims
Showing the top 50 of 217 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →