Inventor · disambiguated record
Sundeep Chadha
Also filed as: CHADHA SUNDEEP
81 granted patents·11 pending applications·189 citations·filing 2003–2023
99Inventor score
Top patents by PatentIndex Score
92 records- 0196US9367322B1Age based fast instruction issueIBM·Filed 2015·Granted Jun 14, 2016·18 cites·20 claims
- 0295US11163571B1Fusion to enhance early address generation of load instructions in a microprocessorIBM·Filed 2020·Granted Nov 2, 2021·4 cites·20 claims
- 0391US10042770B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2016·Granted Aug 7, 2018·6 cites·7 claims
- 0491US10037229B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2016·Granted Jul 31, 2018·6 cites·13 claims
- 0591US9983875B2Operation of a multi-slice processor preventing early dependent instruction wakeupIBM·Filed 2016·Granted May 29, 2018·9 cites·17 claims
- 0687US9928128B2In-pipe error scrubbing within a processor coreIBM·Filed 2016·Granted Mar 27, 2018·6 cites·15 claims
- 0787US9740620B2Distributed history buffer flush and restore handling in a parallel slice designIBM·Filed 2015·Granted Aug 22, 2017·5 cites·13 claims
- 0886US10223125B2Linkable issue queue parallel execution slice processing methodIBM·Filed 2018·Granted Mar 5, 2019·3 cites·20 claims
- 0985US9389870B1Age based fast instruction issueIBM·Filed 2015·Granted Jul 12, 2016·3 cites·1 claims
- 1085US9389867B2Speculative finish of instruction execution in a processor coreIBM·Filed 2015·Granted Jul 12, 2016·4 cites·6 claims
- 1182US10209995B2Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructionsIBM·Filed 2014·Granted Feb 19, 2019·5 cites·17 claims
- 1282US10073697B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2016·Granted Sep 11, 2018·2 cites·5 claims
- 1382US9921833B2Determining of validity of speculative load data after a predetermined period of time in a multi-slice processorIBM·Filed 2015·Granted Mar 20, 2018·3 cites·11 claims
- 1482US9747217B2Distributed history buffer flush and restore handling in a parallel slice designIBM·Filed 2015·Granted Aug 29, 2017·3 cites·7 claims
- 1582US7882278B2Utilizing programmable channels for allocation of buffer space and transaction control in data communicationsIBM·Filed 2009·Granted Feb 1, 2011·10 cites·20 claims
- 1682US7493426B2Data communication method and apparatus utilizing programmable channels for allocation of buffer space and transaction controlIBM·Filed 2005·Granted Feb 17, 2009·10 cites·12 claims
- 1781US10133576B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2015·Granted Nov 20, 2018·2 cites·18 claims
- 1880US12061909B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2023·Granted Aug 13, 2024·0 cites·21 claims
- 1979US10409598B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2018·Granted Sep 10, 2019·1 cites·5 claims
- 2079US10133581B2Linkable issue queue parallel execution slice for a processorIBM·Filed 2015·Granted Nov 20, 2018·2 cites·20 claims
- 2179US9384002B2Speculative finish of instruction execution in a processor coreIBM·Filed 2012·Granted Jul 5, 2016·4 cites·8 claims
- 2278US9959121B2Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registersIBM·Filed 2016·Granted May 1, 2018·2 cites·20 claims
- 2377US9959123B2Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessorIBM·Filed 2015·Granted May 1, 2018·2 cites·7 claims
- 2475US9286068B2Efficient usage of a multi-level register file utilizing a register file bypassIBM·Filed 2012·Granted Mar 15, 2016·3 cites·24 claims
- 2574US11734010B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2021·Granted Aug 22, 2023·0 cites·21 claims
- 2674US10067763B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2015·Granted Sep 4, 2018·1 cites·9 claims
- 2774US7080269B2Method and apparatus for implementing power-saving sleep mode in design with multiple clock domainsIBM·Filed 2003·Granted Jul 18, 2006·20 cites·30 claims
- 2873US10268482B2Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instructionIBM·Filed 2015·Granted Apr 23, 2019·2 cites·10 claims
- 2973US10120693B2Fast multi-width instruction issue in parallel slice processorIBM·Filed 2018·Granted Nov 6, 2018·1 cites·20 claims
- 3072US10379867B2Asynchronous flush and restore of distributed history bufferIBM·Filed 2017·Granted Aug 13, 2019·1 cites·20 claims
- 3172US7761825B2Generating testcases based on numbers of testcases previously generatedIBM·Filed 2008·Granted Jul 20, 2010·4 cites·18 claims
- 3272US7051299B2Method for generating reusable behavioral codeIBM·Filed 2003·Granted May 23, 2006·21 cites·22 claims
- 3370US7464354B2Method and apparatus for performing temporal checkingIBM·Filed 2005·Granted Dec 9, 2008·5 cites·6 claims
- 3468US10884742B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2019·Granted Jan 5, 2021·0 cites·9 claims
- 3567US10831481B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2019·Granted Nov 10, 2020·0 cites·14 claims
- 3667US10719056B2Merging status and control data in a reservation stationIBM·Filed 2016·Granted Jul 21, 2020·1 cites·20 claims
- 3767US9983879B2Operation of a multi-slice processor implementing dynamic switching of instruction issuance orderIBM·Filed 2016·Granted May 29, 2018·1 cites·18 claims
- 3867US9971600B2Techniques to wake-up dependent instructions for back-to-back issue in a microprocessorIBM·Filed 2015·Granted May 15, 2018·1 cites·17 claims
- 3965US10175985B2Mechanism for using a reservation station as a scratch registerIBM·Filed 2016·Granted Jan 8, 2019·1 cites·20 claims
- 4065US9971604B2History buffer for multiple-field registersIBM·Filed 2015·Granted May 15, 2018·1 cites·20 claims
- 4164US11150907B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2018·Granted Oct 19, 2021·0 cites·19 claims
- 4264US10496406B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2018·Granted Dec 3, 2019·0 cites·9 claims
- 4363US10268518B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2018·Granted Apr 23, 2019·0 cites·13 claims
- 4463US10255107B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2018·Granted Apr 9, 2019·0 cites·7 claims
- 4562US7853420B2Performing temporal checkingIBM·Filed 2008·Granted Dec 14, 2010·3 cites·6 claims
- 4662US7502966B2Testcase generation via a pool of parameter filesIBM·Filed 2006·Granted Mar 10, 2009·5 cites·14 claims
- 4761US11138050B2Operation of a multi-slice processor implementing a hardware level transfer of an execution threadIBM·Filed 2019·Granted Oct 5, 2021·0 cites·20 claims
- 4861US10942745B2Fast multi-width instruction issue in parallel slice processorIBM·Filed 2018·Granted Mar 9, 2021·0 cites·18 claims
- 4961US9965286B2Age based fast instruction issueIBM·Filed 2017·Granted May 8, 2018·0 cites·1 claims
- 5061US9870231B2Age based fast instruction issueIBM·Filed 2017·Granted Jan 16, 2018·0 cites·1 claims
Showing the top 50 of 92 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →