Inventor · disambiguated record
Susan E. Eisen
Also filed as: EISEN SUSAN · EISEN SUSAN E · EISEN SUSAN ELIZABETH
58 granted patents·2 pending applications·191 citations·filing 1997–2022
98Inventor score
Technology areasG06F
Top patents by PatentIndex Score
60 records- 0198US11144319B1Redistribution of architected states for a processor register fileIBM·Filed 2020·Granted Oct 12, 2021·19 cites·20 claims
- 0292US7467325B2Processor instruction retry recoveryIBM·Filed 2005·Granted Dec 16, 2008·26 cites·12 claims
- 0390US11086630B1Finish exception handling of an instruction completion tableIBM·Filed 2020·Granted Aug 10, 2021·3 cites·20 claims
- 0489US11941398B1Fast mapper restore for flush in processorIBM·Filed 2022·Granted Mar 26, 2024·1 cites·20 claims
- 0586US10073699B2Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architectureIBM·Filed 2015·Granted Sep 11, 2018·5 cites·20 claims
- 0684US8131976B2Tracking effective addresses in an out-of-order processorDOING RICHARD W·Filed 2009·Granted Mar 6, 2012·18 cites·22 claims
- 0784US7827443B2Processor instruction retry recoveryIBM·Filed 2008·Granted Nov 2, 2010·12 cites·19 claims
- 0883US11119772B2Check pointing of accumulator register results in a microprocessorIBM·Filed 2019·Granted Sep 14, 2021·3 cites·18 claims
- 0982US8725993B2Thread transition managementABERNATHY CHRISTOPHER M·Filed 2011·Granted May 13, 2014·4 cites·6 claims
- 1080US10949213B2Logical register recovery within a processorIBM·Filed 2018·Granted Mar 16, 2021·2 cites·20 claims
- 1179US8386753B2Completion arbitration for more than two threads based on resource limitationsIBM·Filed 2009·Granted Feb 26, 2013·9 cites·20 claims
- 1278US10901743B2Speculative execution of both paths of a weakly predicted branch instructionIBM·Filed 2018·Granted Jan 26, 2021·2 cites·20 claims
- 1371US11144364B2Supporting speculative microprocessor instruction executionIBM·Filed 2019·Granted Oct 12, 2021·1 cites·18 claims
- 1471US10761856B2Instruction completion table containing entries that share instruction tagsIBM·Filed 2018·Granted Sep 1, 2020·1 cites·17 claims
- 1570US7278011B2Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion tableIBM·Filed 2004·Granted Oct 2, 2007·14 cites·34 claims
- 1667US10423423B2Efficiently managing speculative finish tracking and error handling for load instructionsIBM·Filed 2015·Granted Sep 24, 2019·1 cites·13 claims
- 1766US11256507B2Thread transition managementIBM·Filed 2019·Granted Feb 22, 2022·0 cites·5 claims
- 1865US10255071B2Method and apparatus for managing a speculative transaction in a processing unitIBM·Filed 2015·Granted Apr 9, 2019·1 cites·20 claims
- 1964US11366671B2Completion mechanism for a microprocessor instruction completion tableIBM·Filed 2020·Granted Jun 21, 2022·0 cites·20 claims
- 2064US11360779B2Logical register recovery within a processorIBM·Filed 2020·Granted Jun 14, 2022·0 cites·20 claims
- 2164US10296339B2Thread transition managementIBM·Filed 2018·Granted May 21, 2019·0 cites·15 claims
- 2262US8261276B2Power-efficient thread priority enablementBOSE PRADIP·Filed 2008·Granted Sep 4, 2012·2 cites·16 claims
- 2361US11327757B2Processor providing intelligent management of values buffered in overlaid architected and non-architected register filesIBM·Filed 2020·Granted May 10, 2022·0 cites·20 claims
- 2461US10055226B2Thread transition managementIBM·Filed 2017·Granted Aug 21, 2018·0 cites·10 claims
- 2559US10725786B2Completion mechanism for a microprocessor instruction completion tableIBM·Filed 2018·Granted Jul 28, 2020·0 cites·20 claims
- 2659US9703561B2Thread transition managementIBM·Filed 2014·Granted Jul 11, 2017·0 cites·20 claims
- 2758US11327766B2Instruction dispatch routingIBM·Filed 2020·Granted May 10, 2022·0 cites·24 claims
- 2857US11775337B2Prioritization of threads in a simultaneous multithreading processor coreIBM·Filed 2021·Granted Oct 3, 2023·0 cites·17 claims
- 2957US10664275B2Speeding up younger store instruction execution after a sync instructionIBM·Filed 2018·Granted May 26, 2020·0 cites·21 claims
- 3057US10528347B2Executing system call vectored instructions in a multi-slice processorIBM·Filed 2018·Granted Jan 7, 2020·0 cites·11 claims
- 3156US10996995B2Saving and restoring a transaction memory stateIBM·Filed 2019·Granted May 4, 2021·0 cites·20 claims
- 3256US6021488AData processing system having an apparatus for tracking a status of an out-of-order operation and method thereofIBM·Filed 1997·Granted Feb 1, 2000·30 cites·22 claims
- 3354US10831489B2Mechanism for completing atomic instructions in a microprocessorIBM·Filed 2018·Granted Nov 10, 2020·0 cites·20 claims
- 3454US10713057B2Mechanism to stop completions using stop codes in an instruction completion tableIBM·Filed 2018·Granted Jul 14, 2020·0 cites·20 claims
- 3554US10048963B2Executing system call vectored instructions in a multi-slice processorIBM·Filed 2016·Granted Aug 14, 2018·0 cites·17 claims
- 3653US10956158B2System and handling of register data in processorsIBM·Filed 2019·Granted Mar 23, 2021·0 cites·15 claims
- 3752US12204902B2Routing instruction results to a register block of a subdivided register file based on register block utilization rateIBM·Filed 2021·Granted Jan 21, 2025·0 cites·15 claims
- 3852US10740140B2Flush-recovery bandwidth in a processorIBM·Filed 2018·Granted Aug 11, 2020·0 cites·20 claims
- 3951US11194578B2Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessorIBM·Filed 2018·Granted Dec 7, 2021·0 cites·18 claims
- 4051US9268598B2Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memoriesBLAINEY ROBERT J·Filed 2012·Granted Feb 23, 2016·0 cites·10 claims
- 4150US11403109B2Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processorIBM·Filed 2018·Granted Aug 2, 2022·0 cites·17 claims
- 4250US11068267B2High bandwidth logical register flush recoveryIBM·Filed 2019·Granted Jul 20, 2021·0 cites·20 claims
- 4350US10977034B2Instruction completion table with ready-to-complete vectorIBM·Filed 2018·Granted Apr 13, 2021·0 cites·19 claims
- 4450US10552165B2Efficiently managing speculative finish tracking and error handling for load instructionsIBM·Filed 2015·Granted Feb 4, 2020·0 cites·7 claims
- 4550US9268599B2Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memoriesIBM·Filed 2013·Granted Feb 23, 2016·0 cites·5 claims
- 4649US11561794B2Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entryIBM·Filed 2021·Granted Jan 24, 2023·0 cites·20 claims
- 4748US11188332B2System and handling of register data in processorsIBM·Filed 2019·Granted Nov 30, 2021·0 cites·17 claims
- 4848US10282205B2Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructionsIBM·Filed 2015·Granted May 7, 2019·0 cites·20 claims
- 4948US6289437B1Data processing system and method for implementing an efficient out-of-order issue mechanismIBM·Filed 1997·Granted Sep 11, 2001·17 cites·51 claims
- 5047US11030018B2On-demand multi-tiered hang buster for SMT microprocessorIBM·Filed 2017·Granted Jun 8, 2021·0 cites·18 claims
Showing the top 50 of 60 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →