Inventor · disambiguated record
Suresh Nagarajan
Also filed as: NAGARAJAN SURESH
15 granted patents·2 pending applications·84 citations·filing 2004–2023
89Inventor score
Top patents by PatentIndex Score
17 records- 0196US10229735B1Block management for dynamic single-level cell buffers in storage devicesINTEL CORP·Filed 2017·Granted Mar 12, 2019·57 cites·25 claims
- 0288US11237732B2Method and apparatus to improve write bandwidth of a block-based multi-level cell nonvolatile memoryINTEL CORP·Filed 2019·Granted Feb 1, 2022·6 cites·16 claims
- 0387US10379782B2Host managed solid state drivecaching using dynamic write accelerationINTEL CORP·Filed 2017·Granted Aug 13, 2019·6 cites·24 claims
- 0479US10650886B2Block management for dynamic single-level cell buffers in storage devicesINTEL CORP·Filed 2019·Granted May 12, 2020·2 cites·18 claims
- 0573US12094545B2Techniques for preventing read disturb in NAND memoryINTEL CORP·Filed 2023·Granted Sep 17, 2024·0 cites·20 claims
- 0672US11769557B2Techniques for preventing read disturb in NAND memoryINTEL CORP·Filed 2019·Granted Sep 26, 2023·2 cites·18 claims
- 0768US11119672B2Dynamic single level cell memory controllerINTEL CORP·Filed 2019·Granted Sep 14, 2021·1 cites·14 claims
- 0856US12014081B2Host managed buffer to store a logical-to physical address table for a solid state driveINTEL CORP·Filed 2020·Granted Jun 18, 2024·0 cites·20 claims
- 0956US7246195B2Data storage management for flash memory devicesINTEL CORP·Filed 2004·Granted Jul 17, 2007·10 cites·23 claims
- 1052US12147286B2Power and thermal management in a solid state driveINTEL CORP·Filed 2020·Granted Nov 19, 2024·0 cites·17 claims
- 1150US10996860B2Method to improve mixed workload performance on storage devices that use cached operationsINTEL CORP·Filed 2018·Granted May 4, 2021·0 cites·15 claims
- 1248US12019558B2Logical to physical address indirection table in a persistent memory in a solid state driveINTEL CORP·Filed 2020·Granted Jun 25, 2024·0 cites·20 claims
- 1348US10877686B2Mass storage device with host initiated buffer flushingINTEL CORP·Filed 2018·Granted Dec 29, 2020·0 cites·20 claims
- 1447US11783893B2Utilizing NAND buffer for DRAM-less multilevel cell programmingINTEL CORP·Filed 2020·Granted Oct 10, 2023·0 cites·20 claims
- 1540US7603531B2Use of a shutdown object to improve initialization performanceINTEL CORP·Filed 2007·Granted Oct 13, 2009·0 cites·12 claims
- 1639US2007100852A1File system management for integrated NOR and NAND flash memoryWANG JEFFREY·Filed 2005·Application pending·0 cites
- 1736US2006294292A1Shared spare block for multiple memory file volumesILLENDULA AJITH K·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →