Inventor · disambiguated record
Subramanian Natarajan
Also filed as: NATARAJAN SUBRAMANIAN
17 granted patents·816 citations·filing 1994–2023
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
17 records- 0195US5604877AMethod and apparatus for resolving return from subroutine instructions in a computer processorINTEL CORP·Filed 1994·Granted Feb 18, 1997·209 cites·28 claims
- 0293US11487632B2Techniques for LIF placement in SAN storage cluster synchronous disaster recoveryNETAPP INC·Filed 2020·Granted Nov 1, 2022·3 cites·20 claims
- 0391US5574871AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1994·Granted Nov 12, 1996·122 cites·17 claims
- 0490US11782805B2Techniques for LIF placement in SAN storage cluster synchronous disaster recoveryNETAPP INC·Filed 2022·Granted Oct 10, 2023·1 cites·20 claims
- 0590US9965363B2Techniques for LIF placement in SAN storage cluster synchronous disaster recoveryNETAPP INC·Filed 2014·Granted May 8, 2018·12 cites·20 claims
- 0686US10769037B2Techniques for LIF placement in san storage cluster synchronous disaster recoveryNETAPP INC·Filed 2018·Granted Sep 8, 2020·3 cites·20 claims
- 0784US5812839ADual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unitINTEL CORP·Filed 1997·Granted Sep 22, 1998·118 cites·32 claims
- 0880US11561935B2Methods for ensuring correctness of file system analytics and devices thereofNETAPP INC·Filed 2021·Granted Jan 24, 2023·1 cites·20 claims
- 0980US5584001ABranch target buffer for dynamically predicting branch instruction outcomes using a predicted branch historyINTEL CORP·Filed 1995·Granted Dec 10, 1996·95 cites·42 claims
- 1079US12339752B2Techniques for LIF placement in san storage cluster synchronous disaster recoveryNETAPP INC·Filed 2023·Granted Jun 24, 2025·0 cites·20 claims
- 1179US5768576AMethod and apparatus for predicting and handling resolving return from subroutine instructions in a computer processorINTEL CORP·Filed 1996·Granted Jun 16, 1998·75 cites·19 claims
- 1270US5577217AMethod and apparatus for a branch target buffer with shared branch pattern tables for associated branch predictionsINTEL CORP·Filed 1996·Granted Nov 19, 1996·60 cites·10 claims
- 1368US5903751AMethod and apparatus for implementing a branch target buffer in CISC processorINTEL CORP·Filed 1997·Granted May 11, 1999·38 cites·3 claims
- 1466US11940954B2Methods for ensuring correctness of file system analytics and devices thereofNETAPP INC·Filed 2023·Granted Mar 26, 2024·0 cites·20 claims
- 1560US5944817AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1998·Granted Aug 31, 1999·27 cites·4 claims
- 1655US5918046AMethod and apparatus for a branch instruction pointer tableINTEL CORP·Filed 1997·Granted Jun 29, 1999·30 cites·20 claims
- 1755US5706492AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1996·Granted Jan 6, 1998·22 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →