Inventor · disambiguated record
Supratim Pal
Also filed as: PAL SUPRATIM
48 granted patents·33 pending applications·134 citations·filing 2012–2025
97Inventor score
Top patents by PatentIndex Score
81 records- 0198US12007935B2Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2020·Granted Jun 11, 2024·11 cites·25 claims
- 0298US11709793B2Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2022·Granted Jul 25, 2023·9 cites·16 claims
- 0398US11361496B2Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2021·Granted Jun 14, 2022·41 cites·23 claims
- 0497US11954063B2Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2023·Granted Apr 9, 2024·2 cites·23 claims
- 0597US11182337B1Computing efficient cross channel operations in parallel computing machines using systolic arraysINTEL CORP·Filed 2020·Granted Nov 23, 2021·9 cites·20 claims
- 0696US11204977B2Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputsINTEL CORP·Filed 2020·Granted Dec 21, 2021·7 cites·20 claims
- 0794US11636174B2Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputsINTEL CORP·Filed 2021·Granted Apr 25, 2023·3 cites·20 claims
- 0894US10423415B2Hierarchical general register file (GRF) for execution blockINTEL CORP·Filed 2017·Granted Sep 24, 2019·9 cites·18 claims
- 0993US10360654B1Software scoreboard information and synchronizationINTEL CORP·Filed 2018·Granted Jul 23, 2019·16 cites·20 claims
- 1091US12242846B2Supporting 8-bit floating point format operands in a computing architectureINTEL CORP·Filed 2024·Granted Mar 4, 2025·1 cites·20 claims
- 1190US11443407B2Sparse matrix optimization mechanismINTEL CORP·Filed 2021·Granted Sep 13, 2022·5 cites·20 claims
- 1290US2024362180A1Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2024·Application pending·0 cites
- 1389US11977885B2Utilizing structured sparsity in systolic arraysINTEL CORP·Filed 2020·Granted May 7, 2024·2 cites·20 claims
- 1485US11669490B2Computing efficient cross channel operations in parallel computing machines using systolic arraysINTEL CORP·Filed 2021·Granted Jun 6, 2023·1 cites·20 claims
- 1585US11507375B2Hierarchical general register file (GRF) for execution blockINTEL CORP·Filed 2021·Granted Nov 22, 2022·1 cites·20 claims
- 1684US11042370B2Instruction and logic for systolic dot product with accumulateINTEL CORP·Filed 2018·Granted Jun 22, 2021·3 cites·20 claims
- 1783US12346694B2Register file for systolic arrayINTEL CORP·Filed 2021·Granted Jul 1, 2025·1 cites·20 claims
- 1883US11127108B2Sparse matrix optimization mechanismINTEL CORP·Filed 2019·Granted Sep 21, 2021·6 cites·12 claims
- 1982US12189571B2Dual pipeline parallel systolic arrayINTEL CORP·Filed 2021·Granted Jan 7, 2025·1 cites·20 claims
- 2080US12405787B2Utilizing structured sparsity in systolic arraysINTEL CORP·Filed 2024·Granted Sep 2, 2025·0 cites·20 claims
- 2180US10698689B2Recompiling GPU code based on spill/fill instructions and number of stall cyclesINTEL CORP·Filed 2018·Granted Jun 30, 2020·2 cites·19 claims
- 2280US2025199863A1Using sparsity metadata to reduce systolic array power consumptionINTEL CORP·Filed 2024·Application pending·0 cites
- 2379US2024427847A1Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputsINTEL CORP·Filed 2024·Application pending·0 cites
- 2477US12039001B2Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputsINTEL CORP·Filed 2023·Granted Jul 16, 2024·0 cites·20 claims
- 2577US2025390307A1Register file for systolic arrayINTEL CORP·Filed 2025·Application pending·0 cites
- 2675US12093213B2Computing efficient cross channel operations in parallel computing machines using systolic arraysINTEL CORP·Filed 2023·Granted Sep 17, 2024·0 cites·20 claims
- 2775US10990409B2Control flow mechanism for execution of graphics processor instructions using active channel packingINTEL CORP·Filed 2017·Granted Apr 27, 2021·2 cites·19 claims
- 2875US2025117360A1Systolic array of arbitrary physical and logical depthINTEL CORP·Filed 2024·Application pending·0 cites
- 2973US2025117359A1Dual pipeline parallel systolic arrayINTEL CORP·Filed 2024·Application pending·0 cites
- 3073US2025199858A1Multiple register allocation sizes for threadsINTEL CORP·Filed 2024·Application pending·0 cites
- 3172US2023297373A1Instruction and logic for systolic dot product with accumulateINTEL CORP·Filed 2023·Application pending·0 cites
- 3272US2025321736A1Supporting 8-bit floating point format operands in a computing architectureINTEL CORP·Filed 2025·Application pending·0 cites
- 3371US11900502B2Compiler assisted register file write reductionINTEL CORP·Filed 2022·Granted Feb 13, 2024·0 cites·20 claims
- 3471US10983794B2Register sharing mechanismINTEL CORP·Filed 2019·Granted Apr 20, 2021·1 cites·21 claims
- 3569US11640297B2Instruction and logic for systolic dot product with accumulateINTEL CORP·Filed 2021·Granted May 2, 2023·0 cites·20 claims
- 3667US12190158B2Using sparsity metadata to reduce systolic array power consumptionINTEL CORP·Filed 2021·Granted Jan 7, 2025·0 cites·20 claims
- 3767US12174783B2Systolic array of arbitrary physical and logical depthINTEL CORP·Filed 2021·Granted Dec 24, 2024·0 cites·20 claims
- 3867US11537403B2Control flow mechanism for execution of graphics processor instructions using active channel packingINTEL CORP·Filed 2021·Granted Dec 27, 2022·0 cites·22 claims
- 3966US12386617B2Gathering payload from arbitrary registers for send messages in a graphics environmentINTEL CORP·Filed 2021·Granted Aug 12, 2025·0 cites·20 claims
- 4066US11669329B2Instructions and logic for vector multiply add with zero skippingINTEL CORP·Filed 2022·Granted Jun 6, 2023·0 cites·20 claims
- 4166US2025231764A1Large integer multiplication enhancements for graphics environmentINTEL CORP·Filed 2025·Application pending·0 cites
- 4264US12399685B2Systolic array having support for output sparsityINTEL CORP·Filed 2021·Granted Aug 26, 2025·0 cites·20 claims
- 4364US12236238B2Large integer multiplication enhancements for graphics environmentINTEL CORP·Filed 2021·Granted Feb 25, 2025·0 cites·22 claims
- 4464US12210905B2Multiple register allocation sizes for threadsINTEL CORP·Filed 2021·Granted Jan 28, 2025·0 cites·20 claims
- 4563US11593069B2Use of a single instruction set architecture (ISA) instruction for vector normalizationINTEL CORP·Filed 2021·Granted Feb 28, 2023·0 cites·21 claims
- 4663US11579878B2Register sharing mechanism to equally allocate disabled thread registers to active threadsINTEL CORP·Filed 2020·Granted Feb 14, 2023·0 cites·19 claims
- 4763US10789071B2Dynamic thread splitting having multiple instruction pointers for the same threadINTEL CORP·Filed 2015·Granted Sep 29, 2020·1 cites·20 claims
- 4862US12375262B2Fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) workloads in a graphics environmentINTEL CORP·Filed 2021·Granted Jul 29, 2025·0 cites·21 claims
- 4962US11321799B2Compiler assisted register file write reductionINTEL CORP·Filed 2019·Granted May 3, 2022·0 cites·26 claims
- 5062US11314515B2Instructions and logic for vector multiply add with zero skippingINTEL CORP·Filed 2019·Granted Apr 26, 2022·0 cites·20 claims
Showing the top 50 of 81 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →