Inventor · disambiguated record
Suneeta Sah
Also filed as: SAH SUNEETA
16 granted patents·3 pending applications·293 citations·filing 1998–2018
93Inventor score
Top patents by PatentIndex Score
19 records- 0197US9934143B2Mapping a physical address differently to different memory devices in a groupINTEL CORP·Filed 2013·Granted Apr 3, 2018·77 cites·19 claims
- 0296US9104595B2Selective remedial action based on category of detected error for a memory readINTEL CORP·Filed 2013·Granted Aug 11, 2015·51 cites·20 claims
- 0394US10146711B2Techniques to access or operate a dual in-line memory module via multiple data channelsINTEL CORP·Filed 2016·Granted Dec 4, 2018·14 cites·27 claims
- 0488US7047374B2Memory read/write reorderingINTEL CORP·Filed 2003·Granted May 16, 2006·87 cites·17 claims
- 0587US8122265B2Power management using adaptive thermal throttlingRADHAKRISHNAN SIVAKUMAR·Filed 2006·Granted Feb 21, 2012·20 cites·22 claims
- 0686US9910604B2Refresh parameter-dependent memory refresh managementINTEL CORP·Filed 2016·Granted Mar 6, 2018·4 cites·17 claims
- 0782US9269436B2Techniques for determining victim row addresses in a volatile memoryINTEL CORP·Filed 2013·Granted Feb 23, 2016·7 cites·25 claims
- 0878US8438410B2Memory power management via dynamic memory operation statesDAVID HOWARD S·Filed 2010·Granted May 7, 2013·5 cites·26 claims
- 0973US9436632B2Accessing data stored in a command/address register deviceINTEL CORP·Filed 2014·Granted Sep 6, 2016·3 cites·20 claims
- 1071US10592445B2Techniques to access or operate a dual in-line memory module via multiple data channelsINTEL CORP·Filed 2018·Granted Mar 17, 2020·2 cites·31 claims
- 1171US9824754B2Techniques for determining victim row addresses in a volatile memoryINTEL CORP·Filed 2016·Granted Nov 21, 2017·3 cites·31 claims
- 1266US9442871B2Accessing data stored in a command/address register deviceBAINS KULJIT S·Filed 2011·Granted Sep 13, 2016·1 cites·20 claims
- 1366US9030903B2Method, apparatus and system for providing a memory refreshBAINS KULJIT S·Filed 2012·Granted May 12, 2015·3 cites·26 claims
- 1463US9269417B2Memory refresh managementINTEL CORP·Filed 2013·Granted Feb 23, 2016·2 cites·25 claims
- 1554US2016379690A1Accessing data stored in a command/address register deviceINTEL CORP·Filed 2016·Application pending·0 cites
- 1644US7500029B2Maximal length packetsINTEL CORP·Filed 2004·Granted Mar 3, 2009·0 cites·26 claims
- 1744US2019042162A1Back-end memory channel that resides between first and second dimm slots and applications thereofINTEL CORP·Filed 2018·Application pending·0 cites
- 1841US6145062ASelective conflict write flushINTEL CORP·Filed 1998·Granted Nov 7, 2000·14 cites·13 claims
- 1935US2014244922A1Multi-purpose register programming via per dram addressability modeBAINS KULJIT S·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →