Inventor · disambiguated record
Sung-Yen Yeh
Also filed as: YEH SUNG-YEN
18 granted patents·4 pending applications·128 citations·filing 2013–2024
91Inventor score
Top patents by PatentIndex Score
22 records- 0197US11068637B1Systems and methods for context aware circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jul 20, 2021·9 cites·20 claims
- 0297US8826212B2Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formedTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 2, 2014·112 cites·20 claims
- 0394US11853676B2Layout context-based cell timing characterizationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Dec 26, 2023·2 cites·20 claims
- 0489US11531802B2Layout context-based cell timing characterizationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 20, 2022·5 cites·20 claims
- 0588US2024395622A1Integrated circuit in hybrid row height structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0687US2024332083A1Semiconductor device in hybrid row height structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0784US12369389B2Integrated circuit in hybrid row height structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jul 22, 2025·0 cites·20 claims
- 0884US2025124210A1Layout context-based cell timing characterizationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0982US12210811B2Layout context-based cell timing characterizationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jan 28, 2025·0 cites·20 claims
- 1082US2025086371A1Systems and methods for context aware circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1180US12175180B2Systems and methods for context aware circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Dec 24, 2024·0 cites·20 claims
- 1279US12074069B2Semiconductor device and integrated circuit in hybrid row height structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 27, 2024·0 cites·20 claims
- 1379US11791213B2Integrated circuit in hybrid row height structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Oct 17, 2023·0 cites·20 claims
- 1473US11355395B2Integrated circuit in hybrid row height structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 7, 2022·0 cites·20 claims
- 1571US11816413B2Systems and methods for context aware circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Nov 14, 2023·0 cites·20 claims
- 1667US11783106B2Circuit testing and manufacture using multiple timing librariesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Oct 10, 2023·0 cites·20 claims
- 1763US10977402B2Circuit testing and manufacture using multiple timing librariesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Apr 13, 2021·0 cites·20 claims
- 1860US11003820B2Method of determining a worst case in timing analysisTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted May 11, 2021·0 cites·20 claims
- 1957US10503849B2Circuit testing and manufacture using multiple timing librariesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 10, 2019·0 cites·20 claims
- 2054US10776545B2Method of determing a worst case in timing analysisTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Sep 15, 2020·0 cites·17 claims
- 2147US10747924B2Method for manufacturing integrated circuit with aid of pattern based timing database indicating aging effectTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Aug 18, 2020·0 cites·20 claims
- 2245US10176284B2Semiconductor circuit design and manufacture methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jan 8, 2019·0 cites·20 claims
Join the waitlist — get patent alerts
Get an alert when Sung-Yen Yeh files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →