Inventor · disambiguated record
Swadesh Choudhary
Also filed as: CHOUDHARY SWADESH
30 granted patents·20 pending applications·35 citations·filing 2016–2025
94Inventor score
Top patents by PatentIndex Score
50 records- 0194US10534687B2Method and system for cache agent trace and captureINTEL CORP·Filed 2017·Granted Jan 14, 2020·16 cites·20 claims
- 0293US12360934B2Parameter exchange for a die-to-die interconnectINTEL CORP·Filed 2022·Granted Jul 15, 2025·2 cites·20 claims
- 0391US12332826B2Die-to-die interconnectINTEL CORP·Filed 2022·Granted Jun 17, 2025·2 cites·20 claims
- 0487US12481614B2Standard interfaces for die to die (D2D) interconnect stacksINTEL CORP·Filed 2022·Granted Nov 25, 2025·1 cites·20 claims
- 0587US12353305B2Compliance and debug testing of a die-to-die interconnectINTEL CORP·Filed 2022·Granted Jul 8, 2025·1 cites·20 claims
- 0686US11770138B2Encoder and decoder of forward error correction (FEC) codecINTEL CORP·Filed 2020·Granted Sep 26, 2023·2 cites·25 claims
- 0786US11698879B2Flexible on-die fabric interfaceINTEL CORP·Filed 2020·Granted Jul 11, 2023·2 cites·25 claims
- 0885US11281562B2Method and system for cache agent trace and captureINTEL CORP·Filed 2019·Granted Mar 22, 2022·3 cites·12 claims
- 0983US11762802B2Streaming fabric interfaceINTEL CORP·Filed 2020·Granted Sep 19, 2023·2 cites·21 claims
- 1081US11818058B2Shared resources for multiple communication trafficsINTEL CORP·Filed 2021·Granted Nov 14, 2023·1 cites·22 claims
- 1179US2025370945A1Optimized transmission of priority packets via universal chiplet interconnect express (ucie) sideband linkCHOUDHARY SWADESH·Filed 2025·Application pending·0 cites
- 1273US2025123989A1Optimized transmission and broadcasting of priority packets and critical events via ucie-sidebandCHOUDHARY SWADESH·Filed 2024·Application pending·0 cites
- 1372US12244326B2Encoder and decoder of forward error correction (FEC) codecINTEL CORP·Filed 2023·Granted Mar 4, 2025·0 cites·20 claims
- 1472US12111783B2Flexible on-die fabric interfaceINTEL CORP·Filed 2023·Granted Oct 8, 2024·0 cites·20 claims
- 1572US11294850B2System, apparatus and method for increasing bandwidth of edge-located agents of an integrated circuitINTEL CORPORAITON·Filed 2019·Granted Apr 5, 2022·2 cites·8 claims
- 1671US10860515B2Integrated input/output managementINTEL CORP·Filed 2018·Granted Dec 8, 2020·1 cites·18 claims
- 1770US2025321913A1Logical physical layer interface specification support for pcie 6.0, cxl 3.0, and upi 3.0 protocolsINTEL CORP·Filed 2025·Application pending·0 cites
- 1869US12505065B2On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHYINTEL CORP·Filed 2023·Granted Dec 23, 2025·0 cites·20 claims
- 1967US2025370947A1Memory protocols over off-package interconnectsCHOUDHARY SWADESH·Filed 2025·Application pending·0 cites
- 2064US12222881B2Logical physical layer interface specification support for PCie 6.0, cxl 3.0, and UPI 3.0 protocolsINTEL CORP·Filed 2021·Granted Feb 11, 2025·0 cites·19 claims
- 2164US2025225024A1Forward error correction and cyclic redundancy check mechanisms for latency-critical coherency and memory interconnectsINTEL CORP·Filed 2025·Application pending·0 cites
- 2263US11971841B2Link layer-PHY interface adapterINTEL CORP·Filed 2020·Granted Apr 30, 2024·0 cites·20 claims
- 2362US12189470B2Forward error correction and cyclic redundancy check mechanisms for latency-critical coherency and memory interconnectsINTEL CORP·Filed 2020·Granted Jan 7, 2025·0 cites·23 claims
- 2461US12499019B2Retimers to extend a die-to-die interconnectINTEL CORP·Filed 2022·Granted Dec 16, 2025·0 cites·20 claims
- 2560US12373279B2Selection of processing mode for receiver circuitINTEL CORP·Filed 2021·Granted Jul 29, 2025·0 cites·14 claims
- 2660US12362306B2Clock-gating in die-to-die (D2D) interconnectsINTEL CORP·Filed 2022·Granted Jul 15, 2025·0 cites·20 claims
- 2758US12468597B2Valid signal for latency sensitive die-to-die (D2D) interconnectsINTEL CORP·Filed 2022·Granted Nov 11, 2025·0 cites·21 claims
- 2856US12321305B2Sideband interface for die-to-die interconnectsINTEL CORP·Filed 2022·Granted Jun 3, 2025·0 cites·20 claims
- 2955US12332752B2Hardware logging for lane margining and characterizationINTEL CORP·Filed 2021·Granted Jun 17, 2025·0 cites·20 claims
- 3055US11088967B2Shared resources for multiple communication trafficsINTEL CORP·Filed 2019·Granted Aug 10, 2021·0 cites·20 claims
- 3155US2025123990A1On-package memory with universal chiplet interconnect expressDAS SHARMA DEBENDRA·Filed 2024·Application pending·0 cites
- 3254US12405912B2Link initialization training and bring up for die-to-die interconnectINTEL CORP·Filed 2022·Granted Sep 2, 2025·0 cites·20 claims
- 3354US2023258716A1Techniques to perform semiconductor testingINTEL CORP·Filed 2023·Application pending·0 cites
- 3453US2024345983A1Apparatus, system, and method of communicating management transport packets over a universal chiplet interconnect express linkMUTHRASANALLUR SRIDHAR·Filed 2024·Application pending·0 cites
- 3553US2023342323A1Streaming fabric interfaceALI MOHANNAD FAHIM·Filed 2023·Application pending·0 cites
- 3652US2022327084A1Die-to-die interconnect protocol layerINTEL CORP·Filed 2022·Application pending·0 cites
- 3752US2025284653A1Interconnect architecture enabling path diversity for strongly ordered messagesINTEL CORP·Filed 2024·Application pending·0 cites
- 3852US2023237168A1Cxl-cache/mem protocol interface (cpi) latency reduction mechanismCHOUDHARY SWADESH·Filed 2023·Application pending·0 cites
- 3952US2025274399A1Bandwidth scaling knobs for pcie/cxl.io using unordered io as primary vehicleDAS SHARMA DEBENDRA·Filed 2025·Application pending·0 cites
- 4051US12032500B2System, apparatus and method for controlling traffic in a fabricINTEL CORP·Filed 2020·Granted Jul 9, 2024·0 cites·16 claims
- 4151US2023230923A1Microelectronic die including swappable phy circuitry and semiconductor package including sameINTEL CORP·Filed 2022·Application pending·0 cites
- 4248US2022342841A1Die-to-die adapterCHOUDHARY SWADESH·Filed 2022·Application pending·0 cites
- 4347US10514990B2Mission-critical computing architectureINTEL CORP·Filed 2017·Granted Dec 24, 2019·0 cites·25 claims
- 4446US12457271B2System, apparatus and method for handling multi-protocol traffic in data link layer circuitryINTEL CORP·Filed 2020·Granted Oct 28, 2025·0 cites·19 claims
- 4545US2022271912A1Clock phase management for die-to-die (d2d) interconnectPASDAST GERALD·Filed 2022·Application pending·0 cites
- 4644US2021013999A1Latency-Optimized Mechanisms for Handling Errors or Mis-Routed Packets for Computer BusesINTEL CORP·Filed 2020·Application pending·0 cites
- 4744US2019236038A1Buffered interconnect for highly scalable on-die fabricCHOUDHARY SWADESH·Filed 2018·Application pending·0 cites
- 4843US12298833B2Performance level control in a data processing apparatusINTEL CORP·Filed 2020·Granted May 13, 2025·0 cites·19 claims
- 4941US2020242042A1System, Apparatus and Method for Performing a Remote Atomic Operation Via an InterfaceSVENNEBRING JONAS·Filed 2020·Application pending·0 cites
- 5038US2017269959A1Method, apparatus and system to send transactions without trackingINTEL CORP·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →