Inventor · disambiguated record
Sylvain Ouimet
Also filed as: OUIMET SYLVAIN · OUIMET SYLVAIN S E
16 granted patents·1 pending application·189 citations·filing 1996–2020
93Inventor score
Top patents by PatentIndex Score
17 records- 0192US8421217B2Achieving mechanical and thermal stability in a multi-chip packageCASEY JON A·Filed 2012·Granted Apr 16, 2013·19 cites·19 claims
- 0292US8202765B2Achieving mechanical and thermal stability in a multi-chip packageCASEY JON A·Filed 2009·Granted Jun 19, 2012·28 cites·22 claims
- 0390US8290008B2Silicon carrier optoelectronic packagingANDRY PAUL S·Filed 2009·Granted Oct 16, 2012·18 cites·12 claims
- 0488US5781682ALow-cost packaging for parallel optical computer linkIBM·Filed 1996·Granted Jul 14, 1998·72 cites·15 claims
- 0586US8559474B2Silicon carrier optoelectronic packagingANDRY PAUL S·Filed 2012·Granted Oct 15, 2013·9 cites·6 claims
- 0681US10374322B2Antenna packaging solutionIBM·Filed 2017·Granted Aug 6, 2019·3 cites·10 claims
- 0777US10615511B2Antenna packaging solutionIBM·Filed 2019·Granted Apr 7, 2020·2 cites·10 claims
- 0869US7498198B2Structure and method for stress reduction in flip chip microelectronic packages using underfill materials with spatially varying propertiesIBM·Filed 2007·Granted Mar 3, 2009·5 cites·7 claims
- 0961US6137158ALeadframe and leadframe assembly for parallel optical computer linkIBM·Filed 1998·Granted Oct 24, 2000·18 cites·7 claims
- 1059US6414386B1Method to reduce number of wire-bond loop heights versus the total quantity of power and signal ringsIBM·Filed 2000·Granted Jul 2, 2002·9 cites·7 claims
- 1155US9219051B2Laminate peripheral clamping to control microelectronic module BSM warpageIBM·Filed 2013·Granted Dec 22, 2015·1 cites·12 claims
- 1253US11211262B2Electronic apparatus having inter-chip stiffenerIBM·Filed 2020·Granted Dec 28, 2021·0 cites·19 claims
- 1349US6605526B1Wirebond passivation pad connection using heated capillaryIBM·Filed 2000·Granted Aug 12, 2003·4 cites·17 claims
- 1448US7771541B2Method of removing metallic, inorganic and organic contaminants from chip passivation layer surfacesIBM·Filed 2007·Granted Aug 10, 2010·0 cites·19 claims
- 1542US2010218894A1Method of Removing Metallic, Inorganic and Organic Contaminants From Chip Passivation Layer SurfacesIBM·Filed 2010·Application pending·0 cites
- 1641US6946746B2Method to reduce number of wire-bond loop heights versus the total quantity of power and signal ringsIBM·Filed 2004·Granted Sep 20, 2005·1 cites·6 claims
- 1736US6737296B2Method to reduce number of wire-bond loop heights versus the total quantity of power and signal ringsIBM·Filed 2002·Granted May 18, 2004·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →