Inventor · disambiguated record
Szuya Liao
Also filed as: LIAO SZUYA · LIAO SZUYA S
61 granted patents·140 pending applications·108 citations·filing 2013–2025
98Inventor score
Top patents by PatentIndex Score
201 records- 0197US9882027B2Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regionsINTEL CORP·Filed 2014·Granted Jan 30, 2018·12 cites·8 claims
- 0296US11640988B2Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regionsINTEL CORP·Filed 2021·Granted May 2, 2023·2 cites·23 claims
- 0396US9831306B2Self-aligned gate edge and local interconnect and method to fabricate sameINTEL CORP·Filed 2013·Granted Nov 28, 2017·29 cites·45 claims
- 0494US11056492B1Dense memory arrays utilizing access transistors with back-side contactsINTEL CORP·Filed 2019·Granted Jul 6, 2021·9 cites·18 claims
- 0594US10319812B2Self-aligned gate edge and local interconnect and method to fabricate sameINTEL CORP·Filed 2017·Granted Jun 11, 2019·9 cites·30 claims
- 0692US12119271B1Backside gate contact, backside gate etch stop layer, and methods of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Oct 15, 2024·1 cites·20 claims
- 0791US12132079B2Bonding and isolation techniques for stacked transistor structuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Oct 29, 2024·1 cites·20 claims
- 0891US10461177B2Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regionsINTEL CORP·Filed 2018·Granted Oct 29, 2019·4 cites·7 claims
- 0990US12336235B2Semiconductor device having isolation structure formed of low-k dielectric material and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jun 17, 2025·1 cites·14 claims
- 1090US11127841B2Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regionsINTEL CORP·Filed 2019·Granted Sep 21, 2021·3 cites·9 claims
- 1188US2024405101A1Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regionsINTEL CORP·Filed 2024·Application pending·0 cites
- 1287US12131954B1Selective epitaxy process for the formation of CFET local interconnectionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Oct 29, 2024·1 cites·20 claims
- 1386US12218225B1Radical treatment in supercritical fluid for gate dielectric quality improvement to CFET structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Feb 4, 2025·0 cites·20 claims
- 1486US11183592B2Field effect transistor with a hybrid gate spacer including a low-k dielectric materialINTEL CORP·Filed 2016·Granted Nov 23, 2021·4 cites·17 claims
- 1585US12027417B2Source or drain structures with high germanium concentration capping layerINTEL CORP·Filed 2020·Granted Jul 2, 2024·2 cites·16 claims
- 1685US10453967B2Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire deviceINTEL CORP·Filed 2015·Granted Oct 22, 2019·3 cites·18 claims
- 1784US12224326B2Contact architecture for capacitance reduction and satisfactory contact resistanceINTEL CORP·Filed 2023·Granted Feb 11, 2025·0 cites·24 claims
- 1884US11869889B2Self-aligned gate endcap (SAGE) architectures without fin end gapINTEL CORP·Filed 2019·Granted Jan 9, 2024·4 cites·22 claims
- 1984US11043492B2Self-aligned gate edge trigate and finFET devicesINTEL CORP·Filed 2016·Granted Jun 22, 2021·4 cites·16 claims
- 2083US10790354B2Self-aligned gate edge and local interconnectINTEL CORP·Filed 2019·Granted Sep 29, 2020·2 cites·20 claims
- 2183US10720508B2Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride cappingINTEL CORP·Filed 2015·Granted Jul 21, 2020·3 cites·15 claims
- 2282US12094955B2Confined epitaxial regions for semiconductor devicesINTEL CORP·Filed 2023·Granted Sep 17, 2024·0 cites·20 claims
- 2381US2025318270A1Backside gate contact, backside gate etch stop layer, and methods of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2481US2025366185A1P-dipole material for stacked transistorsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2581US2025142935A1Self-aligned gate endcap (sage) architectures with reduced capINTEL CORP·Filed 2024·Application pending·0 cites
- 2681US2025357124A1N-dipole material for stacked transistorsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2781US2025359317A1Cfet with asymmetric source/drain featuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2880US10396176B2Selective gate spacers for semiconductor devicesINTEL CORP·Filed 2014·Granted Aug 27, 2019·3 cites·23 claims
- 2980US10243080B2Selective deposition utilizing sacrificial blocking layers for semiconductor devicesINTEL CORP·Filed 2014·Granted Mar 26, 2019·3 cites·20 claims
- 3080US2025022936A1Self-aligned gate endcap (sage) architectures with reduced capINTEL CORP·Filed 2024·Application pending·0 cites
- 3180US2025359280A1Bottom-up metal gate for stacked device structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3279US2025344468A1Middle dielectric isolation in complementary field-effect transistor devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3379US2025351569A1Dipole-first approach to fabricate a top-tier device of a complementary field effect transistor (cfet)TAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3479US2025316306A1Static random-access memory (sram) device and related sram-based compute-in-memory devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3579US2025366161A1Vertically stacked complementary field effect transistors and methods of fabrication thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3679US2025344503A1NFET AND PFET WITH DIFFERENT FIN NUMBERS IN FinFET BASED CFETTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3779US2025359173A1Stacked multi-gate device with barrier layersTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3878US11217582B2Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal wallsINTEL CORP·Filed 2018·Granted Jan 4, 2022·2 cites·13 claims
- 3978US2025169092A1Radical Treatment in Supercritical Fluid for Gate Dielectric Quality Improvement to CFET StructureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 4078US2025357111A1Dielectric densificationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4178US2025364477A1Semiconductor device and method having high-kappa bonding layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4277US11824097B2Contact architecture for capacitance reduction and satisfactory contact resistanceINTEL CORP·Filed 2022·Granted Nov 21, 2023·0 cites·20 claims
- 4377US10971600B2Selective gate spacers for semiconductor devicesINTEL CORP·Filed 2019·Granted Apr 6, 2021·1 cites·16 claims
- 4477US2023178594A1Self-aligned gate edge and local interconnectDAEDALUS PRIME LLC·Filed 2022·Application pending·0 cites
- 4577US2025351490A1Stacked Multi-Gate Device With Reduced Contact Resistance And Methods For Forming The SameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4677US2025351548A1Dielectric materials for stacked transistor structures and related methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4777US2025351563A1Complementary field effect transistor with hybrid nanostructureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4877US2025359292A1Gate Patterning for Stacked Device StructureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4977US2025343089A1Heat dissipation in semiconductor devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 5077US2025351570A1Stacked complementary finfet process and deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
Showing the top 50 of 201 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →