Inventor · disambiguated record
Takeki Osanai
Also filed as: OSANAI TAKEKI
16 granted patents·3 pending applications·144 citations·filing 1997–2013
92Inventor score
Top patents by PatentIndex Score
19 records- 0186US7302527B2Systems and methods for executing load instructions that avoid order violationsIBM·Filed 2004·Granted Nov 27, 2007·47 cites·32 claims
- 0279US7607059B2Systems and methods for improved scan testing fault coverageTOSHIBA KK·Filed 2006·Granted Oct 20, 2009·10 cites·22 claims
- 0373US6360298B1Load/store instruction control circuit of microprocessor and load/store instruction control methodTOSHIBA KK·Filed 2000·Granted Mar 19, 2002·29 cites·16 claims
- 0472US7464242B2Method of load/store dependencies detection with dynamically changing address lengthIBM·Filed 2005·Granted Dec 9, 2008·6 cites·14 claims
- 0567US7240183B2System and method for detecting instruction dependencies in multiple phasesTOSHIBA KK·Filed 2005·Granted Jul 3, 2007·5 cites·21 claims
- 0664US7376816B2Method and systems for executing load instructions that achieve sequential load consistencyIBM·Filed 2004·Granted May 20, 2008·8 cites·7 claims
- 0763US7769985B2Load address dependency mechanism system and method in a high frequency, low power processor systemIBM·Filed 2008·Granted Aug 3, 2010·2 cites·9 claims
- 0863US7730290B2Systems for executing load instructions that achieve sequential load consistencyIBM·Filed 2008·Granted Jun 1, 2010·2 cites·13 claims
- 0962US7302530B2Method of updating cache state information where stores only read the cache state information upon entering the queueIBM·Filed 2004·Granted Nov 27, 2007·8 cites·26 claims
- 1054US7631149B2Systems and methods for providing fixed-latency data access in a memory system having multi-level cachesTOSHIBA KK·Filed 2006·Granted Dec 8, 2009·1 cites·21 claims
- 1151US7725686B2Systems and methods for processing buffer data retirement conditionsHABUSHIKI KAISHA TOSHIBA·Filed 2006·Granted May 25, 2010·1 cites·12 claims
- 1248US7689776B2Method and system for efficient cache locking mechanismTOSHIBA KK·Filed 2005·Granted Mar 30, 2010·0 cites·14 claims
- 1347US7363468B2Load address dependency mechanism system and method in a high frequency, low power processor systemIBM·Filed 2004·Granted Apr 22, 2008·1 cites·5 claims
- 1446US7346624B2Systems and methods for processing buffer data retirement conditionsTOSHIBA KK·Filed 2004·Granted Mar 18, 2008·0 cites·26 claims
- 1546US2010146214A1Method and system for efficient cache locking mechanismOSANAI TAKEKI·Filed 2010·Application pending·0 cites
- 1643US2014351778A1Lsi design apparatus and method of designing lsiTOSHIBA KK·Filed 2013·Application pending·0 cites
- 1742US6389527B1Microprocessor allowing simultaneous instruction execution and DMA transferTOSHIBA KK·Filed 1999·Granted May 14, 2002·17 cites·20 claims
- 1839US2007022277A1Method and system for an enhanced microprocessorIWAMURA KENJI·Filed 2005·Application pending·0 cites
- 1938US6327665B1Processor with power consumption limiting functionTOSHIBA KK·Filed 1997·Granted Dec 4, 2001·7 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →