Inventor · disambiguated record
Tat Hin Tan
Also filed as: TAN TAT HIN
21 granted patents·3 pending applications·73 citations·filing 2003–2025
93Inventor score
Top patents by PatentIndex Score
24 records- 0196US11652026B2Micro through-silicon via for transistor density scalingINTEL CORP·Filed 2022·Granted May 16, 2023·2 cites·20 claims
- 0295US10903142B2Micro through-silicon via for transistor density scalingINTEL CORP·Filed 2019·Granted Jan 26, 2021·8 cites·22 claims
- 0390US2025385161A1Micro through-silicon via for transistor density scalingINTEL CORP·Filed 2025·Application pending·0 cites
- 0488US2024429131A1Micro through-silicon via for transistor density scalingINTEL CORP·Filed 2024·Application pending·0 cites
- 0584US12112997B2Micro through-silicon via for transistor density scalingINTEL CORP·Filed 2023·Granted Oct 8, 2024·0 cites·20 claims
- 0683US12080628B2Micro through-silicon via for transistor density scalingINTEL CORP·Filed 2023·Granted Sep 3, 2024·0 cites·20 claims
- 0782US10223483B1Methods for determining resistive-capacitive component design targets for radio-frequency circuitryINTEL CORP·Filed 2016·Granted Mar 5, 2019·7 cites·19 claims
- 0882US10200046B1High resolution and low power interpolator for delay chainINTEL CORP·Filed 2017·Granted Feb 5, 2019·4 cites·18 claims
- 0982US8239732B2Error correction coding in flash memory devicesTAN TAT HIN·Filed 2007·Granted Aug 7, 2012·25 cites·20 claims
- 1081US11398415B2Stacked through-silicon vias for multi-device packagesINTEL CORP·Filed 2019·Granted Jul 26, 2022·3 cites·18 claims
- 1181US10198545B1Systems and methods for extraction of electrical specifications from prelayout simulationsALTERA CORP·Filed 2016·Granted Feb 5, 2019·7 cites·20 claims
- 1281US9443567B1High speed sense amplifier latch with low power rail-to-rail input common mode rangeINTEL CORP·Filed 2015·Granted Sep 13, 2016·6 cites·20 claims
- 1375US11393741B2Micro through-silicon via for transistor density scalingINTEL CORP·Filed 2021·Granted Jul 19, 2022·0 cites·11 claims
- 1466US10333689B2High speed sense amplifier latch with low power rail-to-rail input common mode rangeINTEL CORP·Filed 2016·Granted Jun 25, 2019·2 cites·26 claims
- 1560US10110225B1Integrated circuit with an increased signal bandwidth input/output (I/O) circuitINTEL CORP·Filed 2016·Granted Oct 23, 2018·1 cites·15 claims
- 1660US9793888B2Techniques for enabling and disabling transistor legs in an output driver circuitALTERA CORP·Filed 2016·Granted Oct 17, 2017·1 cites·17 claims
- 1759US12469541B2Offset calibration method and apparatus for high bandwidth memory 3 (HBM3)SKYECHIP SDN BHD·Filed 2024·Granted Nov 11, 2025·0 cites·10 claims
- 1857US11373694B1Generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory deviceSKYECHIP SDN BHD·Filed 2021·Granted Jun 28, 2022·0 cites·13 claims
- 1957US10714163B2Methods for mitigating transistor aging to improve timing margins for memory interface signalsINTEL CORP·Filed 2019·Granted Jul 14, 2020·1 cites·20 claims
- 2051US12422883B2System and a method for aligning a programmable clock or strobeSKYECHIP SDN BHD·Filed 2023·Granted Sep 23, 2025·0 cites·10 claims
- 2151US6967532B2Offset-compensated self-biased differential amplifierINTEL CORP·Filed 2003·Granted Nov 22, 2005·6 cites·27 claims
- 2249US2025317046A1Circuitry system and method for regulating voltage thereof using dynamic decoupling capacitorSKYECHIP SDN BHD·Filed 2024·Application pending·0 cites
- 2334US10224911B1Dual signal protocol input/output (I/O) buffer circuitALTERA CORP·Filed 2016·Granted Mar 5, 2019·0 cites·19 claims
- 2431US11575383B2Clocking system and a method of clock synchronizationSKYECHIP SDN BHD·Filed 2021·Granted Feb 7, 2023·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →