Inventor · disambiguated record
Takehiko Tsuchiya
Also filed as: TSUCHIYA TAKEHIKO
10 granted patents·2 pending applications·69 citations·filing 2000–2011
87Inventor score
Top patents by PatentIndex Score
12 records- 0175US6449750B1Design verification device, method and memory media for integrated circuitsTOSHIBA KK·Filed 2000·Granted Sep 10, 2002·25 cites·27 claims
- 0273US7908577B2Apparatus and method for analyzing circuit specification description designTOSHIBA KK·Filed 2008·Granted Mar 15, 2011·7 cites·20 claims
- 0372US7519939B2Method and program for supporting register-transfer-level design of semiconductor integrated circuitTOSHIBA KK·Filed 2007·Granted Apr 14, 2009·5 cites·4 claims
- 0467US6851102B2Method and program for supporting register-transfer-level design of semiconductor integrated circuitTOSHIBA KK·Filed 2002·Granted Feb 1, 2005·11 cites·4 claims
- 0559US7107190B1Circuit designing apparatus, circuit designing method, and computer readable recording medium storing a circuit designing programTOSHIBA KK·Filed 2000·Granted Sep 12, 2006·11 cites·16 claims
- 0656US8856556B2System and method for verifying and maintaining consistency between an intended power mode and an actual power mode in a semiconductor integrated circuitTSUCHIYA TAKEHIKO·Filed 2010·Granted Oct 7, 2014·1 cites·20 claims
- 0756US7263478B2System and method for design verificationTOSHIBA KK·Filed 2001·Granted Aug 28, 2007·6 cites·18 claims
- 0853US7219312B2Method and program for supporting register-transfer-level design of semiconductor integrated circuitTOSHIBA KK·Filed 2004·Granted May 15, 2007·3 cites·4 claims
- 0945US8516419B2Verification device of semiconductor integrated circuit, verification method of semiconductor integrated circuit, and computer readable medium storing verification program of semiconductor integrated circuitTSUCHIYA TAKEHIKO·Filed 2009·Granted Aug 20, 2013·0 cites·16 claims
- 1039US2008288902A1Circuit design verification method and apparatus and computer readable mediumTOSHIBA KK·Filed 2008·Application pending·0 cites
- 1136US8700927B2Semiconductor integrated circuit, interconnect, and computer readable medium storing medium storing control programTSUCHIYA TAKEHIKO·Filed 2011·Granted Apr 15, 2014·0 cites·11 claims
- 1233US2003125920A1LSI design verification apparatus, LSI design verification method, and LSI design verification programFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →