Inventor · disambiguated record
Tal Uliel
Also filed as: ULIEL TAL
23 granted patents·9 pending applications·58 citations·filing 2011–2025
93Inventor score
Top patents by PatentIndex Score
32 records- 0191US9606961B2Instruction and logic to provide vector compress and rotate functionalityINTEL CORP·Filed 2012·Granted Mar 28, 2017·14 cites·35 claims
- 0289US10346163B2Matrix computation engineAPPLE INC·Filed 2017·Granted Jul 9, 2019·7 cites·20 claims
- 0387US10877754B2Matrix computation engineAPPLE INC·Filed 2020·Granted Dec 29, 2020·2 cites·20 claims
- 0486US9524168B2Apparatus and method for shuffling floating point or integer valuesOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Dec 20, 2016·9 cites·18 claims
- 0584US10642620B2Computation engine with strided dot productAPPLE INC·Filed 2018·Granted May 5, 2020·3 cites·20 claims
- 0683US9405539B2Providing vector sub-byte decompression functionalityINTEL CORP·Filed 2013·Granted Aug 2, 2016·6 cites·36 claims
- 0780US9851972B2Functional unit for instruction execution pipeline capable of shifting different chunks of a packed data operand by different amountsINTEL CORP·Filed 2017·Granted Dec 26, 2017·2 cites·25 claims
- 0879US10459877B2Instruction and logic to provide vector compress and rotate functionalityINTEL CORP·Filed 2017·Granted Oct 29, 2019·2 cites·20 claims
- 0975US8984499B2Methods to optimize a program loop via vector instructions using a shuffle table and a blend tableULIEL TAL·Filed 2011·Granted Mar 17, 2015·6 cites·17 claims
- 1070US10592239B2Matrix computation engineAPPLE INC·Filed 2019·Granted Mar 17, 2020·1 cites·15 claims
- 1170US9501276B2Instructions and logic to vectorize conditional loopsINTEL CORP·Filed 2012·Granted Nov 22, 2016·2 cites·47 claims
- 1267US9552209B2Functional unit for instruction execution pipeline capable of shifting different chunks of a packed data operand by different amountsINTEL CORP·Filed 2013·Granted Jan 24, 2017·1 cites·20 claims
- 1363US9378017B2Apparatus and method of efficient vector roll operationINTEL CORP·Filed 2012·Granted Jun 28, 2016·2 cites·20 claims
- 1462US9886242B2Methods to optimize a program loop via vector instructions using a shuffle tableINTEL CORP·Filed 2015·Granted Feb 6, 2018·1 cites·21 claims
- 1560US10990401B2Computation engine with strided dot productAPPLE INC·Filed 2020·Granted Apr 27, 2021·0 cites·20 claims
- 1660US10496411B2Functional unit for instruction execution pipeline capable of shifting different chunks of a packed data operand by different amountsINTEL CORP·Filed 2017·Granted Dec 3, 2019·0 cites·25 claims
- 1759US2020241876A1Range Mapping of Input Operands for Transcendental FunctionsAPPLE INC·Filed 2020·Application pending·0 cites
- 1855US2025265082A1Computation engine with sparse matrix instructionAPPLE INC·Filed 2025·Application pending·0 cites
- 1954US9696993B2Instructions and logic to vectorize conditional loopsINTEL CORP·Filed 2016·Granted Jul 4, 2017·0 cites·20 claims
- 2051US2016342417A1Providing vector sub-byte decompression functionalityINTEL CORP·Filed 2016·Application pending·0 cites
- 2149US2019250917A1Range Mapping of Input Operands for Transcendental FunctionsAPPLE INC·Filed 2018·Application pending·0 cites
- 2248US9442731B2Packed two source inter-element shift merge processors, methods, systems, and instructionsINTEL CORP·Filed 2014·Granted Sep 13, 2016·0 cites·25 claims
- 2346US9513918B2Apparatus and method for performing permute operationsOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Dec 6, 2016·0 cites·17 claims
- 2445US10970078B2Computation engine with upsize/interleave and downsize/deinterleave optionsAPPLE INC·Filed 2018·Granted Apr 6, 2021·0 cites·19 claims
- 2545US9495162B2Apparatus and method for performing a permute operationOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Granted Nov 15, 2016·0 cites·17 claims
- 2643US10474463B2Apparatus and method for down conversion of data typesOULD AHMED VALL ELMOUSTAPHA·Filed 2011·Granted Nov 12, 2019·0 cites·12 claims
- 2743US2015186136A1Systems, apparatuses, and methods for expand and compressULIEL TAL·Filed 2013·Application pending·0 cites
- 2843US2015186137A1Systems, apparatuses, and methods for vector bit testULIEL TAL·Filed 2013·Application pending·0 cites
- 2941US2017235516A1Apparatus and method for shuffling floating point or integer valuesINTEL CORP·Filed 2016·Application pending·0 cites
- 3041US2018121199A1Fused Multiply-Add that Accepts Sources at a First Precision and Generates Results at a Second PrecisionAPPLE INC·Filed 2017·Application pending·0 cites
- 3140US9436469B2Methods to optimize a program loop via vector instructions using a shuffle table and a mask store tableULIEL TAL·Filed 2011·Granted Sep 6, 2016·0 cites·20 claims
- 3238US2017177348A1Instruction and Logic for Compression and RotationINTEL CORP·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →