Inventor · disambiguated record
Tain-Shun Wu
Also filed as: WU TAIN-SHUN
6 granted patents·452 citations·filing 1995–1997
88Inventor score
Files withIND TECH RES INST6
Top patents by PatentIndex Score
6 records- 0194US5637900ALatchup-free fully-protected CMOS on-chip ESD protection circuitIND TECH RES INST·Filed 1995·Granted Jun 10, 1997·144 cites·16 claims
- 0288US5850159AHigh and low speed output buffer with controlled slew rateIND TECH RES INST·Filed 1997·Granted Dec 15, 1998·63 cites·14 claims
- 0388US5754380ACMOS output buffer with enhanced high ESD protection capabilityIND TECH RES INST·Filed 1995·Granted May 19, 1998·79 cites·14 claims
- 0484US5852315AN-sided polygonal cell layout for multiple cell transistorIND TECH RES INST·Filed 1997·Granted Dec 22, 1998·73 cites·33 claims
- 0584US5572394ACMOS on-chip four-LVTSCR ESD protection schemeIND TECH RES INST·Filed 1995·Granted Nov 5, 1996·63 cites·6 claims
- 0678US5757242ALow power consumption oscillators with output level shiftersIND TECH RES INST·Filed 1996·Granted May 26, 1998·30 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →