Inventor · disambiguated record
Tadanori Yamaguchi
Also filed as: SATO SHUICHI · YAMAGUCHI TADANORI
10 granted patents·1 pending application·388 citations·filing 1977–2001
92Inventor score
Top patents by PatentIndex Score
11 records- 0190US4477310AProcess for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areasTEKTRONIX INC·Filed 1983·Granted Oct 16, 1984·111 cites·7 claims
- 0287US6303413B1Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substratesMAXIM INTEGRATED PRODUCTS·Filed 2000·Granted Oct 16, 2001·61 cites·25 claims
- 0386US4902640AHigh speed double polycide bipolar/CMOS integrated circuit processTEKTRONIX INC·Filed 1987·Granted Feb 20, 1990·66 cites·43 claims
- 0477US4994400AMethod of fabricating a semiconductor device using a tri-layer structure and conductive sidewallsTEKTRONIX INC·Filed 1989·Granted Feb 19, 1991·42 cites·25 claims
- 0574US4229756AUltra high speed complementary MOS deviceTEKTRONIX INC·Filed 1979·Granted Oct 21, 1980·32 cites·8 claims
- 0660US4486266AIntegrated circuit methodTEKTRONIX INC·Filed 1983·Granted Dec 4, 1984·24 cites·14 claims
- 0759US4876214AMethod for fabricating an isolation region in a semiconductor substrateTEKTRONIX INC·Filed 1988·Granted Oct 24, 1989·25 cites·18 claims
- 0849US4261761AMethod of manufacturing sub-micron channel width MOS transistorTEKTRONIX INC·Filed 1979·Granted Apr 14, 1981·12 cites·7 claims
- 0940US4217599ANarrow channel MOS devices and method of manufacturingTEKTRONIX INC·Filed 1977·Granted Aug 12, 1980·8 cites·10 claims
- 1038US4228447ASubmicron channel length MOS inverter with depletion-mode load transistorTEKTRONIX INC·Filed 1979·Granted Oct 14, 1980·7 cites·5 claims
- 1131US2002173092A1Forming devices on a semiconductor substrateFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →